1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA SoC SPDIF Audio Layer
4 *
5 * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
6 * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
7 *
8 * Based on the Allwinner SDK driver, released under the GPL.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/regmap.h>
17 #include <linux/of.h>
18 #include <linux/ioport.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
24 #include <sound/asoundef.h>
25 #include <sound/dmaengine_pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28
29 #define SUN4I_SPDIF_CTL (0x00)
30 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
31 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
32 #define SUN4I_SPDIF_CTL_GEN BIT(1)
33 #define SUN4I_SPDIF_CTL_RESET BIT(0)
34
35 #define SUN4I_SPDIF_TXCFG (0x04)
36 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
37 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
38 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
39 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
40 #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
41 #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
42 #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
43 #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
44 #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
45 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
46 #define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
47
48 #define SUN4I_SPDIF_RXCFG (0x08)
49 #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
50 #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
51 #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
52 #define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
53
54 #define SUN4I_SPDIF_TXFIFO (0x0C)
55
56 #define SUN4I_SPDIF_RXFIFO (0x10)
57
58 #define SUN4I_SPDIF_FCTL (0x14)
59 #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
60 #define SUN4I_SPDIF_FCTL_FTX BIT(17)
61 #define SUN4I_SPDIF_FCTL_FRX BIT(16)
62 #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
63 #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
64 #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
65 #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
66 #define SUN4I_SPDIF_FCTL_TXIM BIT(2)
67 #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
68 #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
69
70 #define SUN50I_H6_SPDIF_FCTL (0x14)
71 #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
72 #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
73 #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
74 #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
75 #define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
76 #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
77 #define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
78 #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
79 #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
80 #define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
81
82 #define SUN4I_SPDIF_FSTA (0x18)
83 #define SUN4I_SPDIF_FSTA_TXE BIT(14)
84 #define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
85 #define SUN4I_SPDIF_FSTA_RXA BIT(6)
86 #define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
87
88 #define SUN4I_SPDIF_INT (0x1C)
89 #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
90 #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
91 #define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
92 #define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
93 #define SUN4I_SPDIF_INT_TXUIEN BIT(6)
94 #define SUN4I_SPDIF_INT_TXOIEN BIT(5)
95 #define SUN4I_SPDIF_INT_TXEIEN BIT(4)
96 #define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
97 #define SUN4I_SPDIF_INT_RXOIEN BIT(1)
98 #define SUN4I_SPDIF_INT_RXAIEN BIT(0)
99
100 #define SUN4I_SPDIF_ISTA (0x20)
101 #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
102 #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
103 #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
104 #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
105 #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
106 #define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
107 #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
108 #define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
109
110 #define SUN8I_SPDIF_TXFIFO (0x20)
111
112 #define SUN4I_SPDIF_TXCNT (0x24)
113
114 #define SUN4I_SPDIF_RXCNT (0x28)
115
116 #define SUN4I_SPDIF_TXCHSTA0 (0x2C)
117 #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
118 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
119 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
120 #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
121 #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
122 #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
123 #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
124 #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
125 #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
126 #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
127 #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
128 #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
129
130 #define SUN4I_SPDIF_TXCHSTA1 (0x30)
131 #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
132 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
133 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
134 #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
135 #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
136
137 #define SUN4I_SPDIF_RXCHSTA0 (0x34)
138 #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
139 #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
140 #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
141 #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
142 #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
143 #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
144 #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
145 #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
146 #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
147 #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
148
149 #define SUN4I_SPDIF_RXCHSTA1 (0x38)
150 #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
151 #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
152 #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
153 #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
154
155 /* Defines for Sampling Frequency */
156 #define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
157 #define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
158 #define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
159 #define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
160 #define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
161 #define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
162 #define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
163 #define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
164 #define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
165 #define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
166 #define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
167
168 /**
169 * struct sun4i_spdif_quirks - Differences between SoC variants.
170 *
171 * @reg_dac_txdata: TX FIFO offset for DMA config.
172 * @has_reset: SoC needs reset deasserted.
173 * @val_fctl_ftx: TX FIFO flush bitmask.
174 */
175 struct sun4i_spdif_quirks {
176 unsigned int reg_dac_txdata;
177 bool has_reset;
178 unsigned int val_fctl_ftx;
179 unsigned int mclk_multiplier;
180 };
181
182 struct sun4i_spdif_dev {
183 struct platform_device *pdev;
184 struct clk *spdif_clk;
185 struct clk *apb_clk;
186 struct reset_control *rst;
187 struct snd_soc_dai_driver cpu_dai_drv;
188 struct regmap *regmap;
189 struct snd_dmaengine_dai_dma_data dma_params_tx;
190 const struct sun4i_spdif_quirks *quirks;
191 spinlock_t lock;
192 };
193
sun4i_spdif_configure(struct sun4i_spdif_dev * host)194 static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
195 {
196 const struct sun4i_spdif_quirks *quirks = host->quirks;
197
198 /* soft reset SPDIF */
199 regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
200
201 /* flush TX FIFO */
202 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
203 quirks->val_fctl_ftx, quirks->val_fctl_ftx);
204
205 /* clear TX counter */
206 regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
207 }
208
sun4i_snd_txctrl_on(struct snd_pcm_substream * substream,struct sun4i_spdif_dev * host)209 static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
210 struct sun4i_spdif_dev *host)
211 {
212 if (substream->runtime->channels == 1)
213 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
214 SUN4I_SPDIF_TXCFG_SINGLEMOD,
215 SUN4I_SPDIF_TXCFG_SINGLEMOD);
216
217 /* SPDIF TX ENABLE */
218 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
219 SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
220
221 /* DRQ ENABLE */
222 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
223 SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
224
225 /* Global enable */
226 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
227 SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
228 }
229
sun4i_snd_txctrl_off(struct snd_pcm_substream * substream,struct sun4i_spdif_dev * host)230 static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
231 struct sun4i_spdif_dev *host)
232 {
233 /* SPDIF TX DISABLE */
234 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
235 SUN4I_SPDIF_TXCFG_TXEN, 0);
236
237 /* DRQ DISABLE */
238 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
239 SUN4I_SPDIF_INT_TXDRQEN, 0);
240
241 /* Global disable */
242 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
243 SUN4I_SPDIF_CTL_GEN, 0);
244 }
245
sun4i_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)246 static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
247 struct snd_soc_dai *cpu_dai)
248 {
249 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
250 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
251
252 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
253 return -EINVAL;
254
255 sun4i_spdif_configure(host);
256
257 return 0;
258 }
259
sun4i_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)260 static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
261 struct snd_pcm_hw_params *params,
262 struct snd_soc_dai *cpu_dai)
263 {
264 int ret = 0;
265 int fmt;
266 unsigned long rate = params_rate(params);
267 u32 mclk_div = 0;
268 unsigned int mclk = 0;
269 u32 reg_val;
270 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
271 struct platform_device *pdev = host->pdev;
272
273 /* Add the PCM and raw data select interface */
274 switch (params_channels(params)) {
275 case 1: /* PCM mode */
276 case 2:
277 fmt = 0;
278 break;
279 case 4: /* raw data mode */
280 fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 switch (params_format(params)) {
287 case SNDRV_PCM_FORMAT_S16_LE:
288 fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
289 break;
290 case SNDRV_PCM_FORMAT_S20_3LE:
291 fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
292 break;
293 case SNDRV_PCM_FORMAT_S24_LE:
294 fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
295 break;
296 default:
297 return -EINVAL;
298 }
299
300 switch (rate) {
301 case 22050:
302 case 44100:
303 case 88200:
304 case 176400:
305 mclk = 22579200;
306 break;
307 case 24000:
308 case 32000:
309 case 48000:
310 case 96000:
311 case 192000:
312 mclk = 24576000;
313 break;
314 default:
315 return -EINVAL;
316 }
317 mclk *= host->quirks->mclk_multiplier;
318
319 ret = clk_set_rate(host->spdif_clk, mclk);
320 if (ret < 0) {
321 dev_err(&pdev->dev,
322 "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
323 return ret;
324 }
325
326 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
327 SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);
328
329 switch (rate) {
330 case 22050:
331 case 24000:
332 mclk_div = 8;
333 break;
334 case 32000:
335 mclk_div = 6;
336 break;
337 case 44100:
338 case 48000:
339 mclk_div = 4;
340 break;
341 case 88200:
342 case 96000:
343 mclk_div = 2;
344 break;
345 case 176400:
346 case 192000:
347 mclk_div = 1;
348 break;
349 default:
350 return -EINVAL;
351 }
352 mclk_div *= host->quirks->mclk_multiplier;
353
354 reg_val = 0;
355 reg_val |= SUN4I_SPDIF_TXCFG_ASS;
356 reg_val |= fmt; /* set non audio and bit depth */
357 reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
358 reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
359 regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
360
361 return 0;
362 }
363
sun4i_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)364 static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
365 struct snd_soc_dai *dai)
366 {
367 int ret = 0;
368 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
369
370 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
371 return -EINVAL;
372
373 switch (cmd) {
374 case SNDRV_PCM_TRIGGER_START:
375 case SNDRV_PCM_TRIGGER_RESUME:
376 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
377 sun4i_snd_txctrl_on(substream, host);
378 break;
379
380 case SNDRV_PCM_TRIGGER_STOP:
381 case SNDRV_PCM_TRIGGER_SUSPEND:
382 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
383 sun4i_snd_txctrl_off(substream, host);
384 break;
385
386 default:
387 ret = -EINVAL;
388 break;
389 }
390 return ret;
391 }
392
sun4i_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)393 static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
394 struct snd_ctl_elem_info *uinfo)
395 {
396 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
397 uinfo->count = 1;
398
399 return 0;
400 }
401
sun4i_spdif_get_status_mask(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)402 static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
403 struct snd_ctl_elem_value *ucontrol)
404 {
405 u8 *status = ucontrol->value.iec958.status;
406
407 status[0] = 0xff;
408 status[1] = 0xff;
409 status[2] = 0xff;
410 status[3] = 0xff;
411 status[4] = 0xff;
412 status[5] = 0x03;
413
414 return 0;
415 }
416
sun4i_spdif_get_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)417 static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419 {
420 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
421 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
422 u8 *status = ucontrol->value.iec958.status;
423 unsigned long flags;
424 unsigned int reg;
425
426 spin_lock_irqsave(&host->lock, flags);
427
428 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®);
429
430 status[0] = reg & 0xff;
431 status[1] = (reg >> 8) & 0xff;
432 status[2] = (reg >> 16) & 0xff;
433 status[3] = (reg >> 24) & 0xff;
434
435 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, ®);
436
437 status[4] = reg & 0xff;
438 status[5] = (reg >> 8) & 0x3;
439
440 spin_unlock_irqrestore(&host->lock, flags);
441
442 return 0;
443 }
444
sun4i_spdif_set_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)445 static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
446 struct snd_ctl_elem_value *ucontrol)
447 {
448 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
449 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
450 u8 *status = ucontrol->value.iec958.status;
451 unsigned long flags;
452 unsigned int reg;
453 bool chg0, chg1;
454
455 spin_lock_irqsave(&host->lock, flags);
456
457 reg = (u32)status[3] << 24;
458 reg |= (u32)status[2] << 16;
459 reg |= (u32)status[1] << 8;
460 reg |= (u32)status[0];
461
462 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
463 GENMASK(31,0), reg, &chg0);
464
465 reg = (u32)status[5] << 8;
466 reg |= (u32)status[4];
467
468 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
469 GENMASK(9,0), reg, &chg1);
470
471 reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
472 if (status[0] & IEC958_AES0_NONAUDIO)
473 reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
474
475 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
476 SUN4I_SPDIF_TXCFG_CHSTMODE |
477 SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
478
479 spin_unlock_irqrestore(&host->lock, flags);
480
481 return chg0 || chg1;
482 }
483
484 static struct snd_kcontrol_new sun4i_spdif_controls[] = {
485 {
486 .access = SNDRV_CTL_ELEM_ACCESS_READ,
487 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
488 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
489 .info = sun4i_spdif_info,
490 .get = sun4i_spdif_get_status_mask
491 },
492 {
493 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
494 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
495 .info = sun4i_spdif_info,
496 .get = sun4i_spdif_get_status,
497 .put = sun4i_spdif_set_status
498 }
499 };
500
sun4i_spdif_soc_dai_probe(struct snd_soc_dai * dai)501 static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
502 {
503 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
504
505 snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
506 snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
507 ARRAY_SIZE(sun4i_spdif_controls));
508
509 return 0;
510 }
511
512 static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
513 .probe = sun4i_spdif_soc_dai_probe,
514 .startup = sun4i_spdif_startup,
515 .trigger = sun4i_spdif_trigger,
516 .hw_params = sun4i_spdif_hw_params,
517 };
518
519 static const struct regmap_config sun4i_spdif_regmap_config = {
520 .reg_bits = 32,
521 .reg_stride = 4,
522 .val_bits = 32,
523 .max_register = SUN4I_SPDIF_RXCHSTA1,
524 };
525
526 #define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
527
528 #define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \
529 SNDRV_PCM_FORMAT_S20_3LE | \
530 SNDRV_PCM_FORMAT_S24_LE)
531
532 static struct snd_soc_dai_driver sun4i_spdif_dai = {
533 .playback = {
534 .channels_min = 1,
535 .channels_max = 2,
536 .rates = SUN4I_RATES,
537 .formats = SUN4I_FORMATS,
538 },
539 .ops = &sun4i_spdif_dai_ops,
540 .name = "spdif",
541 };
542
543 static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
544 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
545 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
546 .mclk_multiplier = 1,
547 };
548
549 static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
550 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
551 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
552 .has_reset = true,
553 .mclk_multiplier = 1,
554 };
555
556 static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
557 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
558 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
559 .has_reset = true,
560 .mclk_multiplier = 4,
561 };
562
563 static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
564 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
565 .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
566 .has_reset = true,
567 .mclk_multiplier = 1,
568 };
569
570 static const struct of_device_id sun4i_spdif_of_match[] = {
571 {
572 .compatible = "allwinner,sun4i-a10-spdif",
573 .data = &sun4i_a10_spdif_quirks,
574 },
575 {
576 .compatible = "allwinner,sun6i-a31-spdif",
577 .data = &sun6i_a31_spdif_quirks,
578 },
579 {
580 .compatible = "allwinner,sun8i-h3-spdif",
581 .data = &sun8i_h3_spdif_quirks,
582 },
583 {
584 .compatible = "allwinner,sun50i-h6-spdif",
585 .data = &sun50i_h6_spdif_quirks,
586 },
587 {
588 .compatible = "allwinner,sun50i-h616-spdif",
589 /* Essentially the same as the H6, but without RX */
590 .data = &sun50i_h6_spdif_quirks,
591 },
592 { /* sentinel */ }
593 };
594 MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
595
596 static const struct snd_soc_component_driver sun4i_spdif_component = {
597 .name = "sun4i-spdif",
598 .legacy_dai_naming = 1,
599 };
600
sun4i_spdif_runtime_suspend(struct device * dev)601 static int sun4i_spdif_runtime_suspend(struct device *dev)
602 {
603 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
604
605 clk_disable_unprepare(host->spdif_clk);
606 clk_disable_unprepare(host->apb_clk);
607
608 return 0;
609 }
610
sun4i_spdif_runtime_resume(struct device * dev)611 static int sun4i_spdif_runtime_resume(struct device *dev)
612 {
613 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
614 int ret;
615
616 ret = clk_prepare_enable(host->spdif_clk);
617 if (ret)
618 return ret;
619 ret = clk_prepare_enable(host->apb_clk);
620 if (ret)
621 clk_disable_unprepare(host->spdif_clk);
622
623 return ret;
624 }
625
sun4i_spdif_probe(struct platform_device * pdev)626 static int sun4i_spdif_probe(struct platform_device *pdev)
627 {
628 struct sun4i_spdif_dev *host;
629 struct resource *res;
630 const struct sun4i_spdif_quirks *quirks;
631 int ret;
632 void __iomem *base;
633
634 dev_dbg(&pdev->dev, "Entered %s\n", __func__);
635
636 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
637 if (!host)
638 return -ENOMEM;
639
640 host->pdev = pdev;
641 spin_lock_init(&host->lock);
642
643 /* Initialize this copy of the CPU DAI driver structure */
644 memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
645 host->cpu_dai_drv.name = dev_name(&pdev->dev);
646
647 /* Get the addresses */
648 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
649 if (IS_ERR(base))
650 return PTR_ERR(base);
651
652 quirks = of_device_get_match_data(&pdev->dev);
653 if (quirks == NULL) {
654 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
655 return -ENODEV;
656 }
657 host->quirks = quirks;
658
659 host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
660 &sun4i_spdif_regmap_config);
661
662 /* Clocks */
663 host->apb_clk = devm_clk_get(&pdev->dev, "apb");
664 if (IS_ERR(host->apb_clk)) {
665 dev_err(&pdev->dev, "failed to get a apb clock.\n");
666 return PTR_ERR(host->apb_clk);
667 }
668
669 host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
670 if (IS_ERR(host->spdif_clk)) {
671 dev_err(&pdev->dev, "failed to get a spdif clock.\n");
672 return PTR_ERR(host->spdif_clk);
673 }
674
675 host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
676 host->dma_params_tx.maxburst = 8;
677 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
678
679 platform_set_drvdata(pdev, host);
680
681 if (quirks->has_reset) {
682 host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
683 NULL);
684 if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
685 ret = -EPROBE_DEFER;
686 dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
687 return ret;
688 }
689 if (!IS_ERR(host->rst))
690 reset_control_deassert(host->rst);
691 }
692
693 ret = devm_snd_soc_register_component(&pdev->dev,
694 &sun4i_spdif_component, &sun4i_spdif_dai, 1);
695 if (ret)
696 return ret;
697
698 pm_runtime_enable(&pdev->dev);
699 if (!pm_runtime_enabled(&pdev->dev)) {
700 ret = sun4i_spdif_runtime_resume(&pdev->dev);
701 if (ret)
702 goto err_unregister;
703 }
704
705 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
706 if (ret)
707 goto err_suspend;
708 return 0;
709 err_suspend:
710 if (!pm_runtime_status_suspended(&pdev->dev))
711 sun4i_spdif_runtime_suspend(&pdev->dev);
712 err_unregister:
713 pm_runtime_disable(&pdev->dev);
714 return ret;
715 }
716
sun4i_spdif_remove(struct platform_device * pdev)717 static void sun4i_spdif_remove(struct platform_device *pdev)
718 {
719 pm_runtime_disable(&pdev->dev);
720 if (!pm_runtime_status_suspended(&pdev->dev))
721 sun4i_spdif_runtime_suspend(&pdev->dev);
722 }
723
724 static const struct dev_pm_ops sun4i_spdif_pm = {
725 SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
726 sun4i_spdif_runtime_resume, NULL)
727 };
728
729 static struct platform_driver sun4i_spdif_driver = {
730 .driver = {
731 .name = "sun4i-spdif",
732 .of_match_table = sun4i_spdif_of_match,
733 .pm = &sun4i_spdif_pm,
734 },
735 .probe = sun4i_spdif_probe,
736 .remove = sun4i_spdif_remove,
737 };
738
739 module_platform_driver(sun4i_spdif_driver);
740
741 MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
742 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
743 MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
744 MODULE_LICENSE("GPL");
745 MODULE_ALIAS("platform:sun4i-spdif");
746