Searched +full:0 +full:x00100 (Results 1 – 25 of 95) sorted by relevance
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23 reg = <0x0 0x00100 0x0 0x14>;
12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR20 #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */21 #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */22 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */24 #define _PAGE_EXEC 0x00010 /* H: SX permission */25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */28 #define _PAGE_GUARDED 0x00080 /* H: G bit */29 #define _PAGE_COHERENT 0x00100 /* H: M bit */[all …]
24 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)38 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)54 #define MALIDP550_SE_IRQ_EOW (1 << 0)58 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)71 #define MALIDP_CFG_VALID (1 << 0)72 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)79 #define MALIDP_REG_STATUS 0x0000080 #define MALIDP_REG_SETIRQ 0x0000481 #define MALIDP_REG_MASKIRQ 0x0000882 #define MALIDP_REG_CLEARIRQ 0x0000c[all …]
90 reg = <0x00100 0x14>;
12 * PCI BAR 0 points to these registers.16 u32 int_status; /* 0x000 */18 #define INT_SUSPEND 0x00001 /* or resume */19 #define INT_USBRESET 0x0000220 #define INT_ENDPOINT0 0x0000421 #define INT_SETUP 0x0000822 #define INT_STATUS 0x0001023 #define INT_STATUSNAK 0x0002024 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */25 # define INT_EP1DATASET 0x00040[all …]
37 #define DPCD_RC00_DPCD_REV 0x0000038 #define DPCD_RC01_MAX_LINK_RATE 0x0000139 #define DPCD_RC02 0x0000240 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x8041 #define DPCD_RC02_TPS3_SUPPORTED 0x4042 #define DPCD_RC02_MAX_LANE_COUNT 0x1f43 #define DPCD_RC03 0x0000344 #define DPCD_RC03_MAX_DOWNSPREAD 0x0145 #define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e48 #define DPCD_LC00_LINK_BW_SET 0x00100[all …]
38 #define DPCD_RC00_DPCD_REV 0x0000039 #define DPCD_RC01_MAX_LINK_RATE 0x0000140 #define DPCD_RC02 0x0000241 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x8042 #define DPCD_RC02_TPS3_SUPPORTED 0x4043 #define DPCD_RC02_MAX_LANE_COUNT 0x1f44 #define DPCD_RC03 0x0000345 #define DPCD_RC03_MAX_DOWNSPREAD 0x0146 #define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e49 #define DPCD_LC00_LINK_BW_SET 0x00100[all …]
18 #define ACTL_CON 0x0019 #define ACTL_RESET 0x0420 #define ACTL_RDSTB 0x0821 #define ACTL_RDST_LENGTH 0x0C22 #define ACTL_RDSTC 0x1023 #define ACTL_RSR 0x1424 #define ACTL_PDSTB 0x1825 #define ACTL_PDST_LENGTH 0x1C26 #define ACTL_PDSTC 0x2027 #define ACTL_PSR 0x24[all …]
20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)50 #define MALIDP550_SE_IRQ_EOW (1 << 0)54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)67 #define MALIDP_CFG_VALID (1 << 0)68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)75 #define MALIDP_REG_STATUS 0x0000076 #define MALIDP_REG_SETIRQ 0x0000477 #define MALIDP_REG_MASKIRQ 0x0000878 #define MALIDP_REG_CLEARIRQ 0x0000c[all …]
18 #define MEMCTRLSTATUS_MAGIC 0x0019 #define MM_MAGIC_VALUE (unsigned char)0x5921 #define MEMCTRLSTATUS_BATTERY 0x0422 #define BATTERY_1_DISABLED 0x0123 #define BATTERY_1_FAILURE 0x0224 #define BATTERY_2_DISABLED 0x0425 #define BATTERY_2_FAILURE 0x0827 #define MEMCTRLSTATUS_MEMORY 0x0728 #define MEM_128_MB 0xfe29 #define MEM_256_MB 0xfc[all …]
7 #define IXGBE_VFCTRL 0x000008 #define IXGBE_VFSTATUS 0x000089 #define IXGBE_VFLINKS 0x0001010 #define IXGBE_VFFRTIMER 0x0004811 #define IXGBE_VFRXMEMWRAP 0x0319012 #define IXGBE_VTEICR 0x0010013 #define IXGBE_VTEICS 0x0010414 #define IXGBE_VTEIMS 0x0010815 #define IXGBE_VTEIMC 0x0010C16 #define IXGBE_VTEIAC 0x00110[all …]
19 #define MEMCTRLSTATUS_MAGIC 0x0020 #define MM_MAGIC_VALUE (unsigned char)0x5922 #define MEMCTRLSTATUS_BATTERY 0x0423 #define BATTERY_1_DISABLED 0x0124 #define BATTERY_1_FAILURE 0x0225 #define BATTERY_2_DISABLED 0x0426 #define BATTERY_2_FAILURE 0x0828 #define MEMCTRLSTATUS_MEMORY 0x0729 #define MEM_128_MB 0xfe30 #define MEM_256_MB 0xfc[all …]
22 #define DM_USER_REQ_MAP_READ 035 #define DM_USER_REQ_MAP_FLAG_FAILFAST_DEV 0x0000136 #define DM_USER_REQ_MAP_FLAG_FAILFAST_TRANSPORT 0x0000237 #define DM_USER_REQ_MAP_FLAG_FAILFAST_DRIVER 0x0000438 #define DM_USER_REQ_MAP_FLAG_SYNC 0x0000839 #define DM_USER_REQ_MAP_FLAG_META 0x0001040 #define DM_USER_REQ_MAP_FLAG_PRIO 0x0002041 #define DM_USER_REQ_MAP_FLAG_NOMERGE 0x0004042 #define DM_USER_REQ_MAP_FLAG_IDLE 0x0008043 #define DM_USER_REQ_MAP_FLAG_INTEGRITY 0x00100[all …]
20 #define REG_CTRL 0x0021 #define REG_CTRL_EN 0x0000122 #define REG_CTRL_SLAVE 0x0000223 #define REG_CTRL_AUTOACK 0x0000424 #define REG_CTRL_AUTOSE 0x0000825 #define REG_CTRL_AUTOSN 0x0001026 #define REG_CTRL_ARBDIS 0x0002027 #define REG_CTRL_GCAMEN 0x0004028 #define REG_CTRL_CLHR__MASK 0x0030029 #define REG_CTRL_BITO__MASK 0x03000[all …]
17 #define REG_CTRL 0x0018 #define REG_CTRL_EN 0x0000119 #define REG_CTRL_SLAVE 0x0000220 #define REG_CTRL_AUTOACK 0x0000421 #define REG_CTRL_AUTOSE 0x0000822 #define REG_CTRL_AUTOSN 0x0001023 #define REG_CTRL_ARBDIS 0x0002024 #define REG_CTRL_GCAMEN 0x0004025 #define REG_CTRL_CLHR__MASK 0x0030026 #define REG_CTRL_BITO__MASK 0x03000[all …]
18 #define MSC01_IC_RST_OFS 0x00008 /* Software reset */19 #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */21 #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */23 #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */25 #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */27 #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */[all …]
33 #define TIFM_MS_STAT_DRQ 0x0400034 #define TIFM_MS_STAT_MSINT 0x0200035 #define TIFM_MS_STAT_RDY 0x0100036 #define TIFM_MS_STAT_CRC 0x0020037 #define TIFM_MS_STAT_TOE 0x0010038 #define TIFM_MS_STAT_EMP 0x0002039 #define TIFM_MS_STAT_FUL 0x0001040 #define TIFM_MS_STAT_CED 0x0000841 #define TIFM_MS_STAT_ERR 0x0000442 #define TIFM_MS_STAT_BRQ 0x00002[all …]
29 #define TIFM_MS_STAT_DRQ 0x0400030 #define TIFM_MS_STAT_MSINT 0x0200031 #define TIFM_MS_STAT_RDY 0x0100032 #define TIFM_MS_STAT_CRC 0x0020033 #define TIFM_MS_STAT_TOE 0x0010034 #define TIFM_MS_STAT_EMP 0x0002035 #define TIFM_MS_STAT_FUL 0x0001036 #define TIFM_MS_STAT_CED 0x0000837 #define TIFM_MS_STAT_ERR 0x0000438 #define TIFM_MS_STAT_BRQ 0x00002[all …]
14 WARN_ON((fieldval & ~field##_MASK) != 0); \23 #define V3D_HUB_AXICFG 0x0000024 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 026 #define V3D_HUB_UIFCFG 0x0000427 #define V3D_HUB_IDENT0 0x0000829 #define V3D_HUB_IDENT1 0x0000c40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)41 # define V3D_HUB_IDENT1_TVER_SHIFT 043 #define V3D_HUB_IDENT2 0x00010[all …]
13 #define DU0_REG_OFFSET 0x0000014 #define DU1_REG_OFFSET 0x3000015 #define DU2_REG_OFFSET 0x4000016 #define DU3_REG_OFFSET 0x7000022 #define DSYSR 0x00000 /* display 1 */28 #define DSYSR_TVM_MASTER (0 << 6)32 #define DSYSR_SCM_INT_NONE (0 << 4)37 #define DSMR 0x0000440 #define DSMR_DIPM_DISP (0 << 25)50 #define DSMR_CDEM_CDE (0 << 13)[all …]
16 #define DU0_REG_OFFSET 0x0000017 #define DU1_REG_OFFSET 0x3000018 #define DU2_REG_OFFSET 0x4000019 #define DU3_REG_OFFSET 0x7000025 #define DSYSR 0x00000 /* display 1 */31 #define DSYSR_TVM_MASTER (0 << 6)35 #define DSYSR_SCM_INT_NONE (0 << 4)40 #define DSMR 0x0000443 #define DSMR_DIPM_DISP (0 << 25)53 #define DSMR_CDEM_CDE (0 << 13)[all …]