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/kernel/linux/linux-4.19/sound/soc/codecs/
Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0 14 20 0
75 reg = <0x80008000 0x2000>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 87 86 0 0>;
98 reg = <0x80006000 0x800>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0 14 20 0
75 reg = <0x80008000 0x2000>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
Dimx28.dtsi45 #size-cells = <0>;
47 cpu@0 {
50 reg = <0>;
58 reg = <0x80000000 0x80000>;
65 reg = <0x80000000 0x3c900>;
72 reg = <0x80000000 0x2000>;
76 reg = <0x80002000 0x2000>;
85 reg = <0x80004000 0x2000>;
89 87 86 0 0>;
100 reg = <0x80006000 0x800>;
[all …]
Ddm816x.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
63 reg = <0x44000000 0x10000>;
71 reg = <0x48180000 0x4000>;
74 ranges = <0 0x48180000 0x4000>;
78 #size-cells = <0>;
87 reg = <0x48140000 0x21000>;
91 ranges = <0 0x48140000 0x21000>;
95 reg = <0x800 0x50a>;
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/
Dsun8i_ui_layer.h22 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x0)
24 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x4)
26 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x8)
28 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0xc)
30 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x10)
32 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x14)
34 (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x18)
35 #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(ch) (0x2000 + 0x1000 * (ch) + 0x80)
36 #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(ch) (0x2000 + 0x1000 * (ch) + 0x84)
37 #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch) (0x2000 + 0x1000 * (ch) + 0x88)
[all …]
Dsun8i_vi_layer.h16 (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x0)
18 (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x4)
20 (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x8)
22 (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0xc + 4 * (plane))
24 (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x18 + 4 * (plane))
25 #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch) (0x2000 + 0x1000 * (ch) + 0xe8)
27 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0)
/kernel/linux/linux-5.10/drivers/clk/axs10x/
Di2s_pll_clock.c22 #define PLL_IDIV_REG 0x0
23 #define PLL_FBDIV_REG 0x4
24 #define PLL_ODIV0_REG 0x8
25 #define PLL_ODIV1_REG 0xC
37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
40 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
41 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/kernel/linux/linux-4.19/drivers/clk/axs10x/
Di2s_pll_clock.c21 #define PLL_IDIV_REG 0x0
22 #define PLL_FBDIV_REG 0x4
23 #define PLL_ODIV0_REG 0x8
24 #define PLL_ODIV1_REG 0xC
36 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
37 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
38 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
39 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
40 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
41 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/devfreq/event/
Dexynos-ppmu.txt25 reg = <0x106a0000 0x2000>;
31 reg = <0x106b0000 0x2000>;
37 reg = <0x106c0000 0x2000>;
43 reg = <0x112a0000 0x2000>;
51 reg = <0x116a0000 0x2000>;
115 reg = <0x10480000 0x2000>;
121 reg = <0x10490000 0x2000>;
127 reg = <0x104a0000 0x2000>;
133 reg = <0x104b0000 0x2000>;
139 reg = <0x104c0000 0x2000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/event/
Dexynos-ppmu.txt34 reg = <0x106a0000 0x2000>;
40 reg = <0x106b0000 0x2000>;
46 reg = <0x106c0000 0x2000>;
52 reg = <0x112a0000 0x2000>;
60 reg = <0x116a0000 0x2000>;
124 reg = <0x10480000 0x2000>;
130 reg = <0x10490000 0x2000>;
136 reg = <0x104a0000 0x2000>;
142 reg = <0x104b0000 0x2000>;
148 reg = <0x104c0000 0x2000>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/actions/
Ds900.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0 0x0>;
29 reg = <0x0 0x1>;
36 reg = <0x0 0x2>;
43 reg = <0x0 0x3>;
54 reg = <0x0 0x1f000000 0x0 0x1000000>;
88 #clock-cells = <0>;
99 reg = <0x0 0xe00f1000 0x0 0x1000>,
100 <0x0 0xe00f2000 0x0 0x2000>,
[all …]
Ds700.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x0 0x0>;
28 reg = <0x0 0x1>;
35 reg = <0x0 0x2>;
42 reg = <0x0 0x3>;
53 reg = <0x0 0x1f000000 0x0 0x1000000>;
87 #clock-cells = <0>;
98 reg = <0x0 0xe00f1000 0x0 0x1000>,
99 <0x0 0xe00f2000 0x0 0x2000>,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h52 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
54 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
56 {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
57 0, 0x2000, 0x38b4, 0xe3a6} },
59 {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
60 0, 0x2568, 0x40de, 0xdd3a} },
62 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
63 0x2000, 0x3b61, 0xe24f} },
66 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
67 0x2568, 0x43ee, 0xdbb2} }
[all …]
/kernel/linux/linux-4.19/drivers/reset/
Dreset-uniphier.c29 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
54 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
55 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
60 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
61 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
62 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
63 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
64 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
65 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
66 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-uniphier.c20 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
45 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
51 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
52 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
53 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
54 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
55 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
56 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
57 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
50 if (ret < 0) in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
63 return 0; in nv40_ram_calc()
74 u32 crtc_mask = 0; in nv40_ram_prog()
79 for (i = 0; i < 2; i++) { in nv40_ram_prog()
80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
81 u32 cnt = 0; in nv40_ram_prog()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
50 if (ret < 0) in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
63 return 0; in nv40_ram_calc()
74 u32 crtc_mask = 0; in nv40_ram_prog()
79 for (i = 0; i < 2; i++) { in nv40_ram_prog()
80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
81 u32 cnt = 0; in nv40_ram_prog()
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dhaps_hs.dts19 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
20 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
24 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
41 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/actions/
Ds700.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
107 reg = <0x0 0xe00f1000 0x0 0x1000>,
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dmii.h10 #define MII_BMCR 0x00
11 #define MII_BMSR 0x01
12 #define MII_PHYSID1 0x02
13 #define MII_PHYSID2 0x03
14 #define MII_ADVERTISE 0x04
15 #define MII_LPA 0x05
16 #define MII_EXPANSION 0x06
17 #define MII_CTRL1000 0x09
18 #define MII_STAT1000 0x0a
19 #define MII_MMD_CTRL 0x0d
[all …]

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