Searched +full:0 +full:xf08 (Results 1 – 25 of 71) sorted by relevance
123
| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | xenvm-4.2.dts | 26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
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| D | ecx-2000.dts | 20 /memreserve/ 0x00000000 0x0001000;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
66 memory@0 {
69 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
75 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
79 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
82 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
83 <1 14 0xf08>,
[all …]
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| D | vexpress-v2p-ca15-tc1.dts | 16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
58 reg = <0 0x2b000000 0 0x1000>;
59 interrupts = <0 85 4>;
66 reg = <0 0x2b0a0000 0 0x1000>;
74 reg = <0 0x2b060000 0 0x1000>;
[all …]
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| D | qcom-apq8084.dtsi | 20 reg = <0xfa00000 0x200000>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
182 interrupts = <1 7 0xf04>;
188 #clock-cells = <0>;
194 #clock-cells = <0>;
201 interrupts = <1 2 0xf08>,
202 <1 3 0xf08>,
203 <1 4 0xf08>,
[all …]
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| D | qcom-ipq4019.dtsi | 27 #address-cells = <0x1>;
28 #size-cells = <0x1>;
32 reg = <0x87e00000 0x080000>;
37 reg = <0x87e80000 0x180000>;
51 #size-cells = <0>;
52 cpu@0 {
58 reg = <0x0>;
60 clock-frequency = <0>;
77 reg = <0x1>;
79 clock-frequency = <0>;
[all …]
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| D | vexpress-v2p-ca15_a7.dts | 16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
59 reg = <0x100>;
68 reg = <0x101>;
77 reg = <0x102>;
104 reg = <0 0x80000000 0 0x40000000>;
109 reg = <0 0x2a490000 0 0x1000>;
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | xenvm-4.2.dts | 26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
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| D | ecx-2000.dts | 9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
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| D | vexpress-v2p-ca15-tc1.dts | 16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
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| D | qcom-apq8084.dtsi | 21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
93 reg = <0x0 0x0>;
188 interrupts = <GIC_PPI 7 0xf04>;
194 #clock-cells = <0>;
200 #clock-cells = <0>;
207 interrupts = <GIC_PPI 2 0xf08>,
208 <GIC_PPI 3 0xf08>,
[all …]
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| D | qcom-ipq4019.dtsi | 21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
67 reg = <0x1>;
69 clock-frequency = <0>;
[all …]
|
| D | vexpress-v2p-ca15_a7.dts | 16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
|
| D | hip04.dtsi | 22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 104 interrupts = <1 13 0xf08>,
105 <1 14 0xf08>,
106 <1 11 0xf08>,
107 <1 10 0xf08>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.txt | 58 interrupts = <1 13 0xf08>,
59 <1 14 0xf08>,
60 <1 11 0xf08>,
61 <1 10 0xf08>;
79 - frame-number: 0 to 7.
96 reg = <0xf0000000 0x1000>;
100 frame-number = <0>
101 interrupts = <0 13 0x8>,
102 <0 14 0x8>;
103 reg = <0xf0001000 0x1000>,
[all …]
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 13 /memreserve/ 0x80000000 0x00010000;
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0 0x0>;
42 cpu-release-addr = <0x0 0x8000fff8>;
48 reg = <0x0 0x1>;
50 cpu-release-addr = <0x0 0x8000fff8>;
56 reg = <0x0 0x2>;
58 cpu-release-addr = <0x0 0x8000fff8>;
64 reg = <0x0 0x3>;
[all …]
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| D | foundation-v8.dtsi | 10 /memreserve/ 0x80000000 0x00010000;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0x0 0x0>;
41 reg = <0x0 0x1>;
47 reg = <0x0 0x2>;
53 reg = <0x0 0x3>;
64 reg = <0x00000000 0x80000000 0 0x80000000>,
65 <0x00000008 0x80000000 0 0x80000000>;
70 interrupts = <1 13 0xf08>,
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 29 #size-cells = <0>;
31 cpu0: cpu@0 {
35 reg = <0x0>;
42 reg = <0x1>;
49 reg = <0x2>;
56 reg = <0x3>;
62 interrupts = <0 170 4>,
63 <0 171 4>,
64 <0 172 4>,
65 <0 173 4>;
[all …]
|
| /kernel/linux/linux-4.19/include/linux/amba/ |
| D | sp810.h | 18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
|
| /kernel/linux/linux-5.10/include/linux/amba/ |
| D | sp810.h | 18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-highbank/ |
| D | sysregs.h | 16 #define HB_SREG_A9_PWR_REQ 0xf00
17 #define HB_SREG_A9_BOOT_STAT 0xf04
18 #define HB_SREG_A9_BOOT_DATA 0xf08
20 #define HB_PWR_SUSPEND 0
25 #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_set_core_pwr()
38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_clear_core_pwr()
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()
71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1043a.dtsi | 32 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen 1 0>;
53 reg = <0x1>;
54 clocks = <&clockgen 1 0>;
63 reg = <0x2>;
64 clocks = <&clockgen 1 0>;
73 reg = <0x3>;
74 clocks = <&clockgen 1 0>;
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
107 interrupts = <0 143 4>,
108 <0 144 4>,
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x2000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
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