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/kernel/linux/linux-5.10/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
51 #define BMCR_RESET 0x8000 /* Reset to default state */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
45 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
59 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
60 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
61 * Lanes B-D are numbered 134-136. */
[all …]
/kernel/linux/linux-4.19/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
51 #define BMCR_RESET 0x8000 /* Reset to default state */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
45 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
53 /* Media-dependent registers. */
54 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
55 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
56 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
57 * Lanes B-D are numbered 134-136. */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_utils.h4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
37 #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
40 /* Many gcc seem to no see through this and fall over :( */
42 #define WARN_ON(x) ({ \
43 bool __i915_warn_cond = (x); \
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
39 #define SPEED_1000 1000
162 /* IRQ Anti-Lost Timer Initial Value Register */
241 /* MAC Half-Duplex Control Register */
[all …]
/kernel/linux/linux-4.19/include/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
52 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
64 * The one exception to IEEE 802.3u is that 100baseT4 is placed
65 * between 100T-full and 100T-half. If your phy does not support
67 * priority order, you will need to roll your own function.
89 * @duplex_lock: Non-zero if duplex is locked at full
111 * settings to phy autonegotiation advertisements for the
139 * to ethtool advertisement settings.
166 * settings to phy autonegotiation advertisements for the
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
66 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
75 #define MIN_VOLT_MV 1000
107 * unstable because we do not know how to configure it properly.
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
[all …]
/kernel/linux/linux-5.10/include/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
65 * The one exception to IEEE 802.3u is that 100baseT4 is placed
66 * between 100T-full and 100T-half. If your phy does not support
68 * priority order, you will need to roll your own function.
90 * @duplex_lock: Non-zero if duplex is locked at full
112 * settings to phy autonegotiation advertisements for the
140 * settings to phy autonegotiation advertisements for the
168 * to ethtool advertisement settings.
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/
Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
29 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
30 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
33 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
34 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
40 /* connector doesn't config any color_format, use RGB444 as default */ in komeda_crtc_get_color_config()
52 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
53 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
57 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
60 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
[all …]
/kernel/linux/linux-5.10/drivers/ide/
Dqd65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1996-2001 Linus Torvalds & author (see below)
7 * Version 0.03 Cleaned auto-tune, added probe
15 * To activate controller support, use "ide0=qd65xx"
20 * Samuel Thibault <samuel.thibault@ens-lyon.org>
40 * I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
41 * or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
42 * -- qd6500 is a single IDE interface
43 * -- qd6580 is a dual IDE interface
51 * base: Timer1
[all …]
/kernel/linux/linux-4.19/drivers/ide/
Dqd65xx.c2 * Copyright (C) 1996-2001 Linus Torvalds & author (see below)
6 * Version 0.03 Cleaned auto-tune, added probe
14 * To activate controller support, use "ide0=qd65xx"
19 * Samuel Thibault <samuel.thibault@ens-lyon.org>
39 * I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
40 * or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
41 * -- qd6500 is a single IDE interface
42 * -- qd6580 is a dual IDE interface
50 * base: Timer1
53 * base+0x01: Config (R/O)
[all …]
/kernel/linux/linux-4.19/drivers/isdn/hisax/
Delsa_ser.c5 * This software may be used and distributed according to the terms
51 u_int val = inb(cs->hw.elsa.base + 8 + offset); in serial_in()
52 debugl1(cs, "in %s %02x", ModemIn[offset], val); in serial_in()
55 return inb(cs->hw.elsa.base + 8 + offset); in serial_in()
63 u_int val = inb(cs->hw.elsa.base + 8 + offset); in serial_inp()
64 debugl1(cs, "inp %s %02x", ModemIn[offset], val); in serial_inp()
66 u_int val = inb_p(cs->hw.elsa.base + 8 + offset); in serial_inp()
67 debugl1(cs, "inP %s %02x", ModemIn[offset], val); in serial_inp()
72 return inb(cs->hw.elsa.base + 8 + offset); in serial_inp()
74 return inb_p(cs->hw.elsa.base + 8 + offset); in serial_inp()
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dsfp-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * struct sfp_bus - internal representation of a sfp bus
50 /* Ubiquiti U-Fiber Instant module claims that support all transceiver in sfp_quirk_ubnt_uf_instant()
52 * modes and set only one mode which module supports: 1000baseX_Full. in sfp_quirk_ubnt_uf_instant()
55 phylink_set(modes, 1000baseX_Full); in sfp_quirk_ubnt_uf_instant()
60 // Alcatel Lucent G-010S-P can operate at 2500base-X, but
66 // Alcatel Lucent G-010S-A can operate at 2500base-X, but
72 // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd
79 .part = "UF-INSTANT",
111 vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); in sfp_lookup_quirk()
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
94 * The first 1MB of GPMC address space is typically mapped to
95 * the internal ROM. Never allocate the first page, to
96 * facilitate bug detection; even if we didn't boot from ROM.
203 /* Structure to save gpmc cs context */
[all …]
/kernel/linux/linux-4.19/drivers/net/phy/
Dsfp-bus.c18 * struct sfp_bus - internal representation of a sfp bus
48 // Alcatel Lucent G-010S-P can operate at 2500base-X, but
54 // Alcatel Lucent G-010S-A can operate at 2500base-X, but
60 // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd
95 vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); in sfp_lookup_quirk()
96 ps = sfp_strlen(id->base.vendor_pn, ARRAY_SIZE(id->base.vendor_pn)); in sfp_lookup_quirk()
99 if (sfp_match(q->vendor, id->base.vendor_name, vs) && in sfp_lookup_quirk()
100 sfp_match(q->part, id->base.vendor_pn, ps)) in sfp_lookup_quirk()
106 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type
107 * @bus: a pointer to the &struct sfp_bus structure for the sfp module
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/common/
Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
8 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
43 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) argument
74 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
75 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
76 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
[all …]
/kernel/linux/linux-4.19/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
62 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
71 #define MIN_VOLT_MV 1000
99 {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
100 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
101 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
102 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
122 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
[all …]
/kernel/linux/linux-4.19/drivers/memory/
Domap-gpmc.c4 * Copyright (C) 2005-2006 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #include <asm/mach-types.h>
39 #define DEVICE_NAME "omap-gpmc"
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
206 /* Structure to save gpmc cs context */
[all …]
/kernel/linux/linux-4.19/arch/mips/alchemy/common/
Dusb.c5 * area. Au1550 has OHCI on different base address. No need to handle
7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
19 #include <asm/mach-au1x00/au1000.h>
27 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
31 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
42 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) argument
73 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
74 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
75 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
77 #define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
59 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_object_blt.c1 // SPDX-License-Identifier: MIT
29 struct drm_i915_private *i915 = to_i915(obj->base.dev); in __perf_fill_blt()
34 ktime_t t[5]; in __perf_fill_blt() local
45 for (pass = 0; pass < ARRAY_SIZE(t); pass++) { in __perf_fill_blt()
46 struct intel_context *ce = engine->kernel_context; in __perf_fill_blt()
62 t[pass] = ktime_sub(t1, t0); in __perf_fill_blt()
68 sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL); in __perf_fill_blt()
70 engine->name, in __perf_fill_blt()
71 obj->base.size >> 10, in __perf_fill_blt()
72 div64_u64(mul_u32_u32(4 * obj->base.size, in __perf_fill_blt()
[all …]

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