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/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/
Ddcss-scaler.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
15 #define REPEAT_EN BIT(4)
32 #define Y_UV_BYTE_SWAP BIT(4)
38 #define CHR_BIT_DEPTH_POS 4
39 #define CHR_BIT_DEPTH_MASK GENMASK(5, 4)
88 struct dcss_scaler_ch ch[3]; member
94 #define PSC_BITS_FOR_PHASE 4
101 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
103 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
[all …]
Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
16 #define SW_SHADOW_LOAD_SEL BIT(4)
25 #define DPR2RTR_YRGB_FIFO_OVFL BIT(4)
33 #define TILE_TYPE_MASK GENMASK(4, 2)
53 #define ROT_FLIP_ORDER_EN BIT(4)
73 #define THRES_LOW_POS 4
74 #define THRES_LOW_MASK GENMASK(6, 4)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
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/kernel/linux/linux-4.19/drivers/dma/
Dmic_x100_dma.h41 #define MIC_DMA_NUM_CHAN 4
44 #define MIC_DMA_DESC_RX_SIZE (128 * 1024 - 4)
49 * DCR is a global register and all others are per-channel.
50 * DCR - bits 0, 2, 4, 6, 8, 10, 12, 14 - enable bits for channels 0 to 7
51 * bits 1, 3, 5, 7, 9, 11, 13, 15 - owner bits for channels 0 to 7
52 * DCAR - bit 24 & 25 interrupt masks for mic owned & host owned channels
53 * DHPR - head of the descriptor ring updated by s/w
54 * DTPR - tail of the descriptor ring updated by h/w
55 * DRAR_LO - lower 32 bits of descriptor ring's mic address
56 * DRAR_HI - 3:0 - remaining 4 bits of descriptor ring's mic address
[all …]
Dmoxart-dma.c14 #include <linux/dma-mapping.h>
31 #include "virt-dma.h"
33 #define APB_DMA_MAX_CHANNEL 4
36 #define REG_OFF_ADDRESS_DEST 4
45 #define APB_DMA_ERR_INT_STS BIT(4)
63 * 001: +1 (Burst=0), +4 (Burst=1)
65 * 011: +4 (Burst=0), +16 (Burst=1)
66 * 101: -1 (Burst=0), -4 (Burst=1)
67 * 110: -2 (Burst=0), -8 (Burst=1)
68 * 111: -4 (Burst=0), -16 (Burst=1)
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/kernel/linux/linux-5.10/drivers/clk/berlin/
Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
67 #define VCO_SPEED_1G86_2G00 VCO_SPEED(4)
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
[all …]
/kernel/linux/linux-4.19/drivers/clk/berlin/
Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
67 #define VCO_SPEED_1G86_2G00 VCO_SPEED(4)
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
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/kernel/linux/linux-5.10/drivers/clocksource/
Dsh_mtu2.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - MTU2
55 #define TSTR -1 /* shared register */
60 #define TSR 4 /* channel register */
75 /* Values 4 to 7 are channel-dependent */
80 #define TCR_TPSC_CH0_TCLKA (4 << 0)
84 #define TCR_TPSC_CH1_TCLKA (4 << 0)
88 #define TCR_TPSC_CH2_TCLKA (4 << 0)
92 #define TCR_TPSC_CH34_P256 (4 << 0)
100 #define TMDR_BFA (1 << 4)
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Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
70 #define TSTR -1 /* shared register */
81 #define TCR_TPSC_CLK1024 (4 << 0)
84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
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/kernel/linux/linux-4.19/drivers/clocksource/
Dsh_mtu2.c2 * SuperH Timer Support - MTU2
59 #define TSTR -1 /* shared register */
64 #define TSR 4 /* channel register */
79 /* Values 4 to 7 are channel-dependent */
84 #define TCR_TPSC_CH0_TCLKA (4 << 0)
88 #define TCR_TPSC_CH1_TCLKA (4 << 0)
92 #define TCR_TPSC_CH2_TCLKA (4 << 0)
96 #define TCR_TPSC_CH34_P256 (4 << 0)
104 #define TMDR_BFA (1 << 4)
108 #define TMDR_MD_PHASE_1 (4 << 0)
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Dsh_tmu.c2 * SuperH Timer Support - TMU
74 #define TSTR -1 /* shared register */
85 #define TCR_TPSC_CLK1024 (4 << 0)
88 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
93 switch (ch->tmu->model) { in sh_tmu_read()
95 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
97 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
104 return ioread16(ch->base + offs); in sh_tmu_read()
106 return ioread32(ch->base + offs); in sh_tmu_read()
109 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, in sh_tmu_write() argument
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/kernel/linux/linux-4.19/arch/unicore32/include/mach/
Dregs-dmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 * Source Addr DMAC_SRCADDR(ch).
39 #define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) argument
41 * Destination Addr DMAC_DESTADDR(ch).
43 #define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) argument
45 * Control Reg DMAC_CONTROL(ch).
47 #define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) argument
49 * Configuration Reg DMAC_CONFIG(ch).
51 #define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) argument
55 * select channel (ch)
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/kernel/linux/linux-5.10/drivers/dma/
Dmoxart-dma.c14 #include <linux/dma-mapping.h>
31 #include "virt-dma.h"
33 #define APB_DMA_MAX_CHANNEL 4
36 #define REG_OFF_ADDRESS_DEST 4
45 #define APB_DMA_ERR_INT_STS BIT(4)
63 * 001: +1 (Burst=0), +4 (Burst=1)
65 * 011: +4 (Burst=0), +16 (Burst=1)
66 * 101: -1 (Burst=0), -4 (Burst=1)
67 * 110: -2 (Burst=0), -8 (Burst=1)
68 * 111: -4 (Burst=0), -16 (Burst=1)
[all …]
/kernel/linux/linux-5.10/drivers/staging/most/dim2/
Dhal.c1 // SPDX-License-Identifier: GPL-2.0
3 * hal.c - DIM2 HAL implementation
6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
25 * Number of 32-bit units for DBR map.
29 * 4: block size is 128, max allocation is 4K
37 /* -------------------------------------------------------------------------- */
50 /* -------------------------------------------------------------------------- */
64 /* -------------------------------------------------------------------------- */
86 /* -------------------------------------------------------------------------- */
126 mask <<= mask_size - 1; in alloc_dbr()
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/kernel/linux/linux-4.19/drivers/staging/most/dim2/
Dhal.c1 // SPDX-License-Identifier: GPL-2.0
3 * hal.c - DIM2 HAL implementation
6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
24 * Number of 32-bit units for DBR map.
28 * 4: block size is 128, max allocation is 4K
36 /* -------------------------------------------------------------------------- */
49 /* -------------------------------------------------------------------------- */
63 /* -------------------------------------------------------------------------- */
85 /* -------------------------------------------------------------------------- */
125 mask <<= mask_size - 1; in alloc_dbr()
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/kernel/linux/linux-5.10/drivers/gpu/ipu-v3/
Dipu-prv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
16 #include <video/imx-ipu-v3.h>
52 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) argument
53 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) argument
54 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) argument
60 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) argument
61 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32)) argument
62 #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32)) argument
63 #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32)) argument
[all …]
Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
34 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
74 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/ipu-v3/
Dipu-prv.h3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
25 #include <video/imx-ipu-v3.h>
61 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) argument
62 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) argument
63 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) argument
69 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) argument
70 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32)) argument
71 #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32)) argument
72 #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32)) argument
73 #define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32)) argument
[all …]
Dipu-cpmem.c3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
9 * http://www.opensource.org/licenses/gpl-license.html
17 #include "ipu-prv.h"
40 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
80 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
99 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
101 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
103 return cpmem->base + ch->num; in ipu_get_cpmem()
106 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
108 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
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/kernel/linux/linux-5.10/arch/x86/crypto/
Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
59 # Add reg to mem using reg-mem add and store
86 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
87 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
115 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
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/kernel/linux/linux-4.19/arch/x86/crypto/
Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
60 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
116 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx25821/
Dcx25821-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include "cx25821-sram.h"
16 #include "cx25821-video.h"
19 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
320 [RISC_WRITECR >> 28] = 4, in cx25821_risc_decode()
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
342 struct cx25821_i2c *bus = i2c_adap->algo_data; in i2c_slave_did_ack()
343 struct cx25821_dev *dev = bus->dev; in i2c_slave_did_ack()
344 return cx_read(bus->reg_stat) & 0x01; in i2c_slave_did_ack()
[all …]
/kernel/linux/linux-4.19/drivers/media/pci/cx25821/
Dcx25821-core.c25 #include "cx25821-sram.h"
26 #include "cx25821-video.h"
29 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
36 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
330 [RISC_WRITECR >> 28] = 4, in cx25821_risc_decode()
342 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
352 struct cx25821_i2c *bus = i2c_adap->algo_data; in i2c_slave_did_ack()
353 struct cx25821_dev *dev = bus->dev; in i2c_slave_did_ack()
354 return cx_read(bus->reg_stat) & 0x01; in i2c_slave_did_ack()
373 /* PLL-A setting for the Audio Master Clock */ in cx25821_registers_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-peri.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "clk-uniphier.h"
9 #define UNIPHIER_PERI_CLK_UART(idx, ch) \ argument
10 UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
13 UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
15 #define UNIPHIER_PERI_CLK_I2C(idx, ch) \ argument
16 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
18 #define UNIPHIER_PERI_CLK_FI2C(idx, ch) \ argument
19 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
21 #define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \ argument
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/kernel/linux/linux-5.10/drivers/scsi/
Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
93 ch_printk(KERN_DEBUG, ch, fmt, ##arg); \
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/kernel/linux/linux-4.19/drivers/scsi/
Dch.c4 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
93 ch_printk(KERN_DEBUG, ch, fmt, ##arg); \
98 ch_printk(level, ch, fmt, ##arg); \
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