| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | s0box.c | 33 static u_char nibtab[] = { 1, 9, 5, 0xd, 3, 0xb, 7, 0xf,
46 n1 = (inb_p(padr + 1) >> 3) & 0x17; in readreg()
48 n2 = (inb_p(padr + 1) >> 3) & 0x17; in readreg()
66 n1 = (inb_p(padr + 1) >> 3) & 0x17; in read_fifo()
68 n2 = (inb_p(padr + 1) >> 3) & 0x17; in read_fifo()
96 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); in ReadISAC()
102 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); in WriteISAC()
108 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
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| D | hfc_2bds0.c | 29 dummyf(struct IsdnCardState *cs, u_char *data, int size) in dummyf() argument
35 ReadReg(struct IsdnCardState *cs, int data, u_char reg) in ReadReg() argument
40 if (cs->hw.hfcD.cip != reg) { in ReadReg()
41 cs->hw.hfcD.cip = reg; in ReadReg()
42 byteout(cs->hw.hfcD.addr | 1, reg); in ReadReg()
44 ret = bytein(cs->hw.hfcD.addr); in ReadReg()
46 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) in ReadReg()
47 debugl1(cs, "t3c RD %02x %02x", reg, ret); in ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); in ReadReg()
55 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value) in WriteReg() argument
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| D | sedlbauer.c | 6 * support for the Sedlbauer ISDN-Controller PC/104 and
11 * Copyright by Marcus Niemann <niemann@www-bib.fh-bielefeld.de>
24 * ---------------------------------------------------------------------
25 * Speed Card ISAC_HSCX DIP-SWITCH
30 * ISDN PC/104 IPAC DIP-SWITCH
66 #define SEDL_SPEED_FAX 3
77 #define SEDL_CHIP_IPAC 3
81 #define SEDL_BUS_PCMCIA 3
89 #define SEDL_HSCX_ISA_HSCX 3
154 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
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| D | elsa.c | 36 {"None", "PC", "PCC-8", "PCC-16", "PCF", "PCF-Pro",
38 "PCMCIA-IPAC" };
41 {"?0?", "?1?", "?2?", "?3?", "?4?", "V2.2",
51 #define ELSA_ALE 3
60 #define ELSA_PCC16 3
83 *** (mehrere Befehle werden durch Bit-Oderung kombiniert) ***
86 /* Config-Register (Read) */
87 #define ELIRQF_TIMER_RUN 0x02 /* Bit 1 des Config-Reg */
88 #define ELIRQF_TIMER_RUN_PCC8 0x01 /* Bit 0 des Config-Reg bei PCC */
89 #define ELSA_IRQ_IDX 0x38 /* Bit 3,4,5 des Config-Reg */
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| D | saphir.c | 29 #define IRQ_REG 3
68 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); in ReadISAC()
74 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
80 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
82 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in ReadISACfifo()
86 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
88 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in WriteISACfifo()
92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
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| D | isar.c | 25 static const u_char faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121, 122, 145, 146};
31 static void isar_setup(struct IsdnCardState *cs);
36 waitforHIA(struct IsdnCardState *cs, int timeout) in waitforHIA() argument
39 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) { in waitforHIA()
41 timeout--; in waitforHIA()
50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, in sendmsg() argument
55 if (!waitforHIA(cs, 4000)) in sendmsg()
58 if (cs->debug & L1_DEB_HSCX) in sendmsg()
59 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len); in sendmsg()
61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); in sendmsg()
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| D | sportster.c | 11 * Thanks to Christian "naddy" Weisgerber (3Com, US Robotics) for documentation
36 return (base + ((off & 0xfc) << 8) + ((off & 3) << 1)); in calc_off()
54 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
56 return (bytein(calc_off(cs->hw.spt.isac, offset))); in ReadISAC()
60 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
62 byteout(calc_off(cs->hw.spt.isac, offset), value); in WriteISAC()
66 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
68 read_fifo(cs->hw.spt.isac, data, size); in ReadISACfifo()
72 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
74 write_fifo(cs->hw.spt.isac, data, size); in WriteISACfifo()
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| D | teles3.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.teles3.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
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| D | hfc_pci.c | 3 * low level driver for CCD's hfc-pci based cards
56 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
64 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2, "Sitecom Europe", "DC-105 ISDN PCI"},
73 release_io_hfcpci(struct IsdnCardState *cs) in release_io_hfcpci() argument
76 cs->hw.hfcpci.pci_io); in release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
79 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in release_io_hfcpci()
81 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
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| D | hscx.c | 22 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
26 HscxVersion(struct IsdnCardState *cs, char *s) in HscxVersion() argument
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; in HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; in HscxVersion()
43 struct IsdnCardState *cs = bcs->cs; in modehscx() local
44 int hscx = bcs->hw.hscx.hscx; in modehscx()
46 if (cs->debug & L1_DEB_HSCX) in modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", in modehscx()
49 bcs->mode = mode; in modehscx()
50 bcs->channel = bc; in modehscx()
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| D | ix1_micro.c | 3 * low level stuff for ITK ix1-micro Rev.2 isdn cards
6 * Author Klaus-Peter Nischke
7 * Copyright by Klaus-Peter Nischke, ITK AG
14 * Klaus-Peter Nischke
32 #define SPECIAL_PORT_OFFSET 3
76 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); in ReadISAC()
82 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
88 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
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| D | isdnl1.c | 130 debugl1(struct IsdnCardState *cs, char *fmt, ...) in debugl1() argument
136 sprintf(tmp, "Card%d ", cs->cardnr + 1); in debugl1()
137 VHiSax_putstatus(cs, tmp, fmt, args); in debugl1()
145 struct PStack *st = fi->userdata; in l1m_debug()
146 struct IsdnCardState *cs = st->l1.hardware; in l1m_debug() local
150 sprintf(tmp, "Card%d ", cs->cardnr + 1); in l1m_debug()
151 VHiSax_putstatus(cs, tmp, fmt, args); in l1m_debug()
156 L1activated(struct IsdnCardState *cs) in L1activated() argument
160 st = cs->stlist; in L1activated()
162 if (test_and_clear_bit(FLG_L1_ACTIVATING, &st->l1.Flags)) in L1activated()
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| D | avm_a1.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.avm.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.avm.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.avm.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); in ReadHSCX()
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| D | hfc_sx.c | 3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
25 /* IRQ-table for CCDs demo board */
33 * ISA-SLOT Signal PIN
46 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
50 0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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| D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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| D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
17 #define CPU_INSTR_PER_JIFFY 3
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
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| /kernel/linux/linux-4.19/arch/m68k/include/asm/ |
| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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| D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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| D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
17 #define CPU_INSTR_PER_JIFFY 3
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
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| /kernel/linux/linux-5.10/drivers/s390/char/ |
| D | raw3270.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define TUBICMD _IO('3', 3) /* set ccw command for fs reads. */
16 #define TUBOCMD _IO('3', 4) /* set ccw command for fs writes. */
17 #define TUBGETI _IO('3', 7) /* get ccw command for fs reads. */
18 #define TUBGETO _IO('3', 8) /* get ccw command for fs writes. */
19 #define TUBSETMOD _IO('3',12) /* FIXME: what does it do ?*/
20 #define TUBGETMOD _IO('3',13) /* FIXME: what does it do ?*/
44 #define TF_INMDT 0xc1 /* Visible, Set-MDT */
55 /* Extended-Highlighting Bytes */
123 return list_empty(&rq->list); in raw3270_request_final()
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| /kernel/linux/linux-4.19/drivers/s390/char/ |
| D | raw3270.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define TUBICMD _IO('3', 3) /* set ccw command for fs reads. */
16 #define TUBOCMD _IO('3', 4) /* set ccw command for fs writes. */
17 #define TUBGETI _IO('3', 7) /* get ccw command for fs reads. */
18 #define TUBGETO _IO('3', 8) /* get ccw command for fs writes. */
19 #define TUBSETMOD _IO('3',12) /* FIXME: what does it do ?*/
20 #define TUBGETMOD _IO('3',13) /* FIXME: what does it do ?*/
44 #define TF_INMDT 0xc1 /* Visible, Set-MDT */
55 /* Extended-Highlighting Bytes */
124 return list_empty(&rq->list); in raw3270_request_final()
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| /kernel/linux/linux-4.19/drivers/isdn/gigaset/ |
| D | capi.c | 31 #define CAPI_CONNECT_ACTIVE_IND_BASELEN (CAPI_MSG_BASELEN + 4 + 3 * 1)
72 #define MAX_HLC_OCTETS 3
76 /* values for bcs->apconnstate */
103 u8 cgpty_buf[MAX_NUMBER_DIGITS + 3];
112 [1] = { "8090A3", NULL }, /* Speech (A-law) */
114 [3] = { "8990", NULL }, /* Restricted digital information */
115 [4] = { "9090A3", NULL }, /* 3,1 kHz audio (A-law) */
123 [17] = { "9090A3", "9184" }, /* Group 2/3 facsimile */
151 static inline void ignore_cstruct_param(struct cardstate *cs, _cstruct param, in ignore_cstruct_param() argument
155 dev_warn(cs->dev, "%s: ignoring unsupported parameter: %s\n", in ignore_cstruct_param()
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
142 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
145 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
150 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
153 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
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| /kernel/linux/linux-4.19/drivers/memory/ |
| D | omap-gpmc.c | 4 * Copyright (C) 2005-2006 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #include <asm/mach-types.h>
39 #define DEVICE_NAME "omap-gpmc"
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
148 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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