| /kernel/linux/linux-5.10/arch/arm/mach-realview/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
35 one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
39 bool "Support ARM1136J(F)-S Tile"
47 bool "Support ARM1176JZ(F)-S Tile"
54 bool "Support Multicore Cortex-A9 Tile"
57 Enable support for the Cortex-A9MPCore tile fitted to the
74 the ARM11MPCore. This platform has an on-board ARM11MPCore and has
75 support for PCI-E and Compact Flash.
79 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mach-realview/ |
| D | Kconfig | 36 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
37 one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
41 bool "Support ARM1136J(F)-S Tile"
49 bool "Support ARM1176JZ(F)-S Tile"
56 bool "Support Multicore Cortex-A9 Tile"
61 Enable support for the Cortex-A9MPCore tile fitted to the
80 the ARM11MPCore. This platform has an on-board ARM11MPCore and has
81 support for PCI-E and Compact Flash.
85 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
92 ARM1176JZF-S.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
[all …]
|
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
|
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
[all …]
|
| D | meson8b.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
63 enable-method = "amlogic,meson8b-smp";
[all …]
|
| D | meson8.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/clock/meson8b-clkc.h>
47 #include <dt-bindings/gpio/meson8-gpio.h>
48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
57 #address-cells = <1>;
58 #size-cells = <0>;
62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
65 enable-method = "amlogic,meson8-smp";
[all …]
|
| D | cx92755.dtsi | 8 * This file is dual-licensed: you can use it either under the terms
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
70 intc: interrupt-controller@f0000040 {
71 compatible = "cnxt,cx92755-ic";
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
[all …]
|
| D | cx92755.dtsi | 8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpus.txt | 13 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
33 - cpus node
41 - #address-cells
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
55 # On ARM v8 64-bit systems value should be set to 2,
58 in the system, #address-cells can be set to 1, since
61 - #size-cells
66 - cpu node
72 - device_type
[all …]
|
| D | pmu.txt | 5 representation in the device tree should be done as under:-
9 - compatible : should be one of
10 "apm,potenza-pmu"
11 "arm,armv8-pmuv3"
12 "arm,cortex-a73-pmu"
13 "arm,cortex-a72-pmu"
14 "arm,cortex-a57-pmu"
15 "arm,cortex-a53-pmu"
16 "arm,cortex-a35-pmu"
17 "arm,cortex-a17-pmu"
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
46 * - loc - location to jump to for soft reset
47 * - hyp - indicate if restart occurs in HYP mode
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mm/ |
| D | proc-v7.S | 2 * linux/arch/arm/mm/proc-v7.S
12 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
18 #include <asm/pgtable-hwdef.h>
22 #include "proc-macros.S"
25 #include "proc-v7-3level.S"
27 #include "proc-v7-2level.S"
49 * - loc - location to jump to for soft reset
50 * - hyp - indicate if restart occurs in HYP mode
79 dsb @ WFI may enter a low-power mode
[all …]
|
| /kernel/linux/linux-4.19/Documentation/arm/sunxi/ |
| D | README | 9 ------------
10 Linux kernel mach directory: arch/arm/mach-sunxi
14 - Allwinner F20 (sun3i)
17 * ARM Cortex-A8 based SoCs
18 - Allwinner A10 (sun4i)
20 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
22 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
24 - Allwinner A10s (sun5i)
26 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
28 - Allwinner A13 / R8 (sun5i)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | sunxi.rst | 10 ------------
11 Linux kernel mach directory: arch/arm/mach-sunxi
16 - Allwinner F20 (sun3i)
20 * ARM Cortex-A8 based SoCs
21 - Allwinner A10 (sun4i)
25 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
28 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
30 - Allwinner A10s (sun5i)
34 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
36 - Allwinner A13 / R8 (sun5i)
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
244 Patch phys-to-virt and virt-to-phys translation functions at
248 This can only be used with non-XIP MMU kernels where the base
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
349 bool "EBSA-110"
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
115 The ARM series is a line of low-power-consumption RISC chip designs
117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
118 manufactured, but legacy ARM-based PC hardware remains popular in
170 ---help---
179 Say Y here if you are building a kernel for an EISA-based machine.
251 Patch phys-to-virt and virt-to-phys translation functions at
255 This can only be used with non-XIP MMU kernels where the base
305 bool "MMU-based Paged Memory Management Support"
308 Select if you want MMU-based virtualised addressing space
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | cpu-imx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
42 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
60 if (mx5_cpu_rev == -1) in mx51_revision()
71 * Dependent on link order - so the assumption is that vfp_init is called
88 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
108 if (mx5_cpu_rev == -1) in mx53_revision()
134 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
138 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | perf_event_v7.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
11 * Cortex-A8 has up to 4 configurable performance counters and
13 * Cortex-A9 has up to 31 configurable performance counters and
55 * - all (taken) branch instructions,
56 * - instructions that explicitly write the PC,
57 * - exception generating instructions.
82 /* ARMv7 Cortex-A8 specific event types */
88 /* ARMv7 Cortex-A9 specific event types */
93 /* ARMv7 Cortex-A5 specific event types */
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/kernel/ |
| D | perf_event_v7.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
11 * Cortex-A8 has up to 4 configurable performance counters and
13 * Cortex-A9 has up to 31 configurable performance counters and
55 * - all (taken) branch instructions,
56 * - instructions that explicitly write the PC,
57 * - exception generating instructions.
82 /* ARMv7 Cortex-A8 specific event types */
88 /* ARMv7 Cortex-A9 specific event types */
93 /* ARMv7 Cortex-A5 specific event types */
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mach-imx/ |
| D | cpu-imx5.c | 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * http://www.opensource.org/licenses/gpl-license.html
25 static int mx5_cpu_rev = -1;
48 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
66 if (mx5_cpu_rev == -1) in mx51_revision()
77 * Dependent on link order - so the assumption is that vfp_init is called
94 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
114 if (mx5_cpu_rev == -1) in mx53_revision()
140 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
144 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | ti-cpufreq.txt | 6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
20 - syscon: A phandle pointing to a syscon node representing the control module
24 --------------------
25 - "vdd-supply", "vbb-supply": to define two regulators for dra7xx
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/cpufreq/ |
| D | ti-cpufreq.txt | 6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs
19 - syscon: A phandle pointing to a syscon node representing the control module
23 --------------------
24 For each opp entry in 'operating-points-v2' table:
[all …]
|