Searched full:exynos_sclk_i2s (Results 1 – 22 of 22) sorted by relevance
20 #define EXYNOS_SCLK_I2S 7 macro
71 <&clock_audss EXYNOS_SCLK_I2S>;
66 <&clock_audss EXYNOS_SCLK_I2S>;
223 <&clock_audss EXYNOS_SCLK_I2S>;
519 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
82 <&clock_audss EXYNOS_SCLK_I2S>;
590 <&clock_audss EXYNOS_SCLK_I2S>;
509 <&clock_audss EXYNOS_SCLK_I2S>;
85 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
80 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
231 <&clock_audss EXYNOS_SCLK_I2S>;
506 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
76 <&clock_audss EXYNOS_SCLK_I2S>;
561 <&clock_audss EXYNOS_SCLK_I2S>;
434 <&clock_audss EXYNOS_SCLK_I2S>;
98 <&clock_audss EXYNOS_SCLK_I2S>,
77 <&clock_audss EXYNOS_SCLK_I2S>;
148 <&clock_audss EXYNOS_SCLK_I2S>;
226 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
222 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()