| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 3 * PCIe host controller driver for Tegra194 SoC
33 #include "pcie-designware.h"
319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
322 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
327 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); in apply_bad_link_workaround() local
346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
350 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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| D | Kconfig | 23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
63 work in host mode. There are two instances of PCIe controller in
71 bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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| D | pci-layerscape.c | 3 * PCIe host controller driver for Freescale Layerscape SoCs
23 #include "pcie-designware.h"
56 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
58 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
68 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
70 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
76 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
79 struct dw_pcie *pci = pcie->pci; in ls_pcie_drop_msg_tlp()
86 static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) in ls_pcie_disable_outbound_atus() argument
91 dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); in ls_pcie_disable_outbound_atus()
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pci-tegra.c | 3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
220 * entries, one entry per PCIe port. These field definitions and desired
315 struct tegra_pcie *pcie; member
331 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
334 writel(value, pcie->afi + offset); in afi_writel()
337 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
339 return readl(pcie->afi + offset); in afi_readl()
342 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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| D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
24 /* PCIe core registers */
122 /* PCIe core controller registers */
130 /* PCIe Central Interrupts Registers */
194 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
196 writel(val, pcie->base + reg); in advk_writel()
199 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
201 return readl(pcie->base + reg); in advk_readl()
204 static int advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
208 val = advk_readl(pcie, CFG_REG); in advk_pcie_link_up()
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| D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
175 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
177 return readl(pcie->breg_base + off); in nwl_bridge_readl()
180 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
182 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
185 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
192 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
51 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
55 #define TLP_CFGWR_DW0(pcie, bus) \ argument
56 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
59 #define TLP_CFG_DW1(pcie, tag, be) \ argument
60 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
88 static inline void cra_writel(struct altera_pcie *pcie, const u32 value, in cra_writel() argument
91 writel_relaxed(value, pcie->cra_base + reg); in cra_writel()
94 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) in cra_readl() argument
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| D | pcie-mobiveil.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
135 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
148 static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value, in csr_writel() argument
151 writel_relaxed(value, pcie->csr_axi_slave_base + reg); in csr_writel()
154 static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg) in csr_readl() argument
156 return readl_relaxed(pcie->csr_axi_slave_base + reg); in csr_readl()
159 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) in mobiveil_pcie_link_up() argument
161 return (csr_readl(pcie, LTSSM_STATUS) & in mobiveil_pcie_link_up()
167 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_valid_device() local
170 if ((bus->number == pcie->root_bus_nr) && (devfn > 0)) in mobiveil_pcie_valid_device()
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| D | pcie-rcar.c | 3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
71 /* PCIe address reg & mask */
149 /* Structure representing the PCIe interface */
160 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val, in rcar_pci_write_reg() argument
163 writel(val, pcie->base + reg); in rcar_pci_write_reg()
166 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie, in rcar_pci_read_reg() argument
169 return readl(pcie->base + reg); in rcar_pci_read_reg()
177 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
180 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
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| D | pcie-cadence.c | 3 // Cadence PCIe controller driver.
8 #include "pcie-cadence.h"
10 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_set_outbound_region() argument
30 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
31 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
33 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
42 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
46 * mode, the PCIe controller may support more than one function. This in cdns_pcie_set_outbound_region()
47 * function number needs to be set properly into the outbound PCIe in cdns_pcie_set_outbound_region()
56 * the PCIe controller will use the captured values for the bus and in cdns_pcie_set_outbound_region()
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| D | pcie-iproc.c | 24 #include "pcie-iproc.h"
95 * iProc PCIe outbound mapping controller specific parameters
142 * iProc PCIe inbound mapping type
156 * iProc PCIe inbound mapping controller specific parameters
228 * iProc PCIe host registers
302 /* iProc PCIe PAXB BCMA registers */
313 /* iProc PCIe PAXB registers */
329 /* iProc PCIe PAXB v2 registers */
357 /* iProc PCIe PAXC v1 registers */
366 /* iProc PCIe PAXC v2 registers */
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| D | Kconfig | 7 bool "Marvell EBU PCIe controller"
14 bool "Aardvark PCIe controller"
19 Add support for Aardvark 64bit PCIe Host Controller. This
23 menu "Cadence PCIe controllers support"
29 bool "Cadence PCIe host controller"
35 Say Y here if you want to support the Cadence PCIe controller in host
36 mode. This PCIe controller may be embedded into many different vendors
40 bool "Cadence PCIe endpoint controller"
45 Say Y here if you want to support the Cadence PCIe controller in
46 endpoint mode. This PCIe controller may be embedded into many
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
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| D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
30 /* PCIe core registers */
121 /* PCIe window configuration */
170 /* PCIe core controller registers */
178 /* PCIe Central Interrupts Registers */
257 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
259 writel(val, pcie->base + reg); in advk_writel()
262 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
264 return readl(pcie->base + reg); in advk_readl()
267 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) in advk_read16() argument
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| D | pci-tegra.c | 3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
271 * entries, one entry per PCIe port. These field definitions and desired
376 struct tegra_pcie *pcie; member
394 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
397 writel(value, pcie->afi + offset); in afi_writel()
400 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
402 return readl(pcie->afi + offset); in afi_readl()
405 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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| D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| D | pcie-iproc.c | 24 #include "pcie-iproc.h"
99 * iProc PCIe outbound mapping controller specific parameters
146 * iProc PCIe inbound mapping type
160 * iProc PCIe inbound mapping controller specific parameters
239 * iProc PCIe host registers
316 /* iProc PCIe PAXB BCMA registers */
327 /* iProc PCIe PAXB registers */
343 /* iProc PCIe PAXB v2 registers */
374 /* iProc PCIe PAXC v1 registers */
383 /* iProc PCIe PAXC v2 registers */
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| D | pcie-brcmstb.c | 37 /* Broadcom STB PCIe Register Offsets */
144 /* PCIe parameters */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
191 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
194 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
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| D | pcie-rcar-host.c | 3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
50 /* Structure representing the PCIe interface */
52 struct rcar_pcie pcie; member
61 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
64 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
74 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
102 *data = rcar_pci_read_reg(pcie, PCICONF(index)); in rcar_pcie_config_access()
104 rcar_pci_write_reg(pcie, *data, PCICONF(index)); in rcar_pcie_config_access()
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| /kernel/linux/linux-5.10/drivers/staging/mt7621-pci/ |
| D | pci-mt7621.c | 12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
66 /* PCIe RC control registers */
92 * struct mt7621_pcie_port - PCIe port information
95 * @pcie: pointer to PCIe host info
106 struct mt7621_pcie *pcie; member
116 * struct mt7621_pcie - PCIe host information
122 * @dev: Pointer to PCIe device
124 * @ports: pointer to PCIe port information
125 * @irq_map: irq mapping info according pcie link status
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
28 #include "pcie-mobiveil.h"
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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| D | pcie-layerscape-gen4.c | 3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_lut_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_readl()
50 static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_lut_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_writel()
56 static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_pf_readl() argument
58 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_readl()
61 static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_pf_writel() argument
64 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_writel()
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| D | pcie-mobiveil.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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| /kernel/linux/linux-4.19/drivers/staging/mt7621-pci/ |
| D | pci-mt7621.c | 35 * support RT2880/RT3883 PCIe
38 * support RT6855/MT7620 PCIe
128 * struct mt7621_pcie_port - PCIe port information
131 * @pcie: pointer to PCIe host info
137 struct mt7621_pcie *pcie; member
142 * struct mt7621_pcie - PCIe host information
148 * @dev: Pointer to PCIe device
149 * @ports: pointer to PCIe port information
164 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) in pcie_read() argument
166 return readl(pcie->base + reg); in pcie_read()
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 3 // Cadence PCIe controller driver.
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
49 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
58 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
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