| /kernel/linux/linux-5.10/drivers/hwmon/ |
| D | bt1-pvt.c | 33 #include "bt1-pvt.h"
50 * to PVT data and vice-versa are following:
152 * Baikal-T1 PVT mode can be updated only when the controller is disabled.
158 static inline void pvt_set_mode(struct pvt_hwmon *pvt, u32 mode) in pvt_set_mode() argument
164 old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); in pvt_set_mode()
165 pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_MODE_MASK | PVT_CTRL_EN, in pvt_set_mode()
176 static inline void pvt_set_trim(struct pvt_hwmon *pvt, u32 trim) in pvt_set_trim() argument
182 old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); in pvt_set_trim()
183 pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_TRIM_MASK | PVT_CTRL_EN, in pvt_set_trim()
187 static inline void pvt_set_tout(struct pvt_hwmon *pvt, u32 tout) in pvt_set_tout() argument
[all …]
|
| D | mr75203.c | 5 * This driver is a hardware monitoring driver for PVT controller
21 /* PVT Common register */
142 struct pvt_device *pvt = dev_get_drvdata(dev); in pvt_read_temp() local
143 struct regmap *t_map = pvt->t_map; in pvt_read_temp()
169 *val = tmp - PVT_G_CONST - pvt->ip_freq; in pvt_read_temp()
179 struct pvt_device *pvt = dev_get_drvdata(dev); in pvt_read_in() local
180 struct regmap *v_map = pvt->v_map; in pvt_read_in()
185 if (channel >= pvt->v_num) in pvt_read_in()
188 vm_idx = pvt->vm_idx[channel]; in pvt_read_in()
253 static int pvt_init(struct pvt_device *pvt) in pvt_init() argument
[all …]
|
| D | bt1-pvt.h | 17 /* Baikal-T1 PVT registers and their bitfields */
61 * PVT sensors-related limits and default values
68 * @PVT_DATA_MIN: Minimal PVT raw data value.
69 * @PVT_DATA_MAX: Maximal PVT raw data value.
78 * activated the PVT IRQ is enabled to be raised after each
105 * enum pvt_sensor_type - Baikal-T1 PVT sensor types (correspond to each PVT
108 * @PVT_TEMP: PVT Temperature sensor.
109 * @PVT_VOLT: PVT Voltage sensor.
110 * @PVT_LVT: PVT Low-Voltage threshold sensor.
111 * @PVT_HVT: PVT High-Voltage threshold sensor.
[all …]
|
| /kernel/linux/linux-4.19/drivers/edac/ |
| D | amd64_edac.c | 86 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
90 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
91 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
93 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
110 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
113 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
126 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
138 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
139 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
150 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
[all …]
|
| D | i7core_edac.c | 398 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) argument
399 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) argument
402 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) argument
403 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) argument
491 struct i7core_pvt *pvt = mci->pvt_info; in get_dimm_config() local
499 pdev = pvt->pci_mcr[0]; in get_dimm_config()
504 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); in get_dimm_config()
505 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); in get_dimm_config()
506 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); in get_dimm_config()
507 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); in get_dimm_config()
[all …]
|
| D | sb_edac.c | 318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
329 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
330 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
793 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) in sbridge_get_tolm() argument
798 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
802 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) in sbridge_get_tohm() argument
806 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
810 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) in ibridge_get_tolm() argument
[all …]
|
| D | amd64_edac.h | 140 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) argument
141 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) argument
142 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) argument
145 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) argument
146 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) argument
147 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) argument
150 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) argument
171 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
193 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) argument
194 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) argument
[all …]
|
| D | i7300_edac.c | 355 struct i7300_pvt *pvt; in i7300_process_error_global() local
361 pvt = mci->pvt_info; in i7300_process_error_global()
364 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
374 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
380 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
390 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
410 struct i7300_pvt *pvt; in i7300_process_fbd_error() local
420 pvt = mci->pvt_info; in i7300_process_fbd_error()
423 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, in i7300_process_fbd_error()
432 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, in i7300_process_fbd_error()
[all …]
|
| D | i5400_edac.c | 438 struct i5400_pvt *pvt; in i5400_get_error_info() local
441 pvt = mci->pvt_info; in i5400_get_error_info()
444 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5400_get_error_info()
457 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
459 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
461 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
465 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
475 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5400_get_error_info()
483 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
485 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
[all …]
|
| D | i5000_edac.c | 388 struct i5000_pvt *pvt; in i5000_get_error_info() local
391 pvt = mci->pvt_info; in i5000_get_error_info()
394 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5000_get_error_info()
406 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
408 pci_read_config_word(pvt->branchmap_werrors, in i5000_get_error_info()
410 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
414 pci_write_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
424 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5000_get_error_info()
432 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
434 pci_read_config_word(pvt->branchmap_werrors, in i5000_get_error_info()
[all …]
|
| D | amd64_edac_inj.c | 9 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_section_show() local
10 return sprintf(buf, "0x%x\n", pvt->injection.section); in amd64_inject_section_show()
24 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_section_store() local
37 pvt->injection.section = (u32) value; in amd64_inject_section_store()
46 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_word_show() local
47 return sprintf(buf, "0x%x\n", pvt->injection.word); in amd64_inject_word_show()
61 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_word_store() local
74 pvt->injection.word = (u32) value; in amd64_inject_word_store()
83 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_ecc_vector_show() local
84 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in amd64_inject_ecc_vector_show()
[all …]
|
| D | e752x_edac.c | 308 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; in ctl_page_to_phys() local
312 if (page < pvt->tolm) in ctl_page_to_phys()
315 if ((page >= 0x100000) && (page < pvt->remapbase)) in ctl_page_to_phys()
318 remap = (page - pvt->tolm) + pvt->remapbase; in ctl_page_to_phys()
320 if (remap < pvt->remaplimit) in ctl_page_to_phys()
324 return pvt->tolm - 1; in ctl_page_to_phys()
334 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; in do_process_ce() local
342 if (pvt->mc_symmetric) { in do_process_ce()
347 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], in do_process_ce()
348 pvt->map[4], pvt->map[5], pvt->map[6], in do_process_ce()
[all …]
|
| D | e7xxx_edac.c | 186 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; in ctl_page_to_phys() local
190 if ((page < pvt->tolm) || in ctl_page_to_phys()
191 ((page >= 0x100000) && (page < pvt->remapbase))) in ctl_page_to_phys()
194 remap = (page - pvt->tolm) + pvt->remapbase; in ctl_page_to_phys()
196 if (remap < pvt->remaplimit) in ctl_page_to_phys()
200 return pvt->tolm - 1; in ctl_page_to_phys()
259 struct e7xxx_pvt *pvt; in e7xxx_get_error_info() local
261 pvt = (struct e7xxx_pvt *)mci->pvt_info; in e7xxx_get_error_info()
262 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); in e7xxx_get_error_info()
263 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); in e7xxx_get_error_info()
[all …]
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| D | amd64_edac.c | 89 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
93 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
94 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
96 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
113 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
116 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
129 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
141 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
142 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
153 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
[all …]
|
| D | dmc520_edac.c | 178 static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset) in dmc520_read_reg() argument
180 return readl(pvt->reg_base + offset); in dmc520_read_reg()
183 static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset) in dmc520_write_reg() argument
185 writel(val, pvt->reg_base + offset); in dmc520_write_reg()
200 static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt, in dmc520_get_dram_ecc_error_count() argument
212 err_low = dmc520_read_reg(pvt, reg_offset_low); in dmc520_get_dram_ecc_error_count()
213 err_high = dmc520_read_reg(pvt, reg_offset_high); in dmc520_get_dram_ecc_error_count()
215 dmc520_write_reg(pvt, 0, reg_offset_low); in dmc520_get_dram_ecc_error_count()
216 dmc520_write_reg(pvt, 0, reg_offset_high); in dmc520_get_dram_ecc_error_count()
224 static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt, in dmc520_get_dram_ecc_error_info() argument
[all …]
|
| D | sb_edac.c | 318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
330 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
331 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
794 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) in sbridge_get_tolm() argument
799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
803 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) in sbridge_get_tohm() argument
807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
811 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) in ibridge_get_tolm() argument
[all …]
|
| D | i7core_edac.c | 396 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) argument
397 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) argument
400 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) argument
401 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) argument
489 struct i7core_pvt *pvt = mci->pvt_info; in get_dimm_config() local
497 pdev = pvt->pci_mcr[0]; in get_dimm_config()
502 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); in get_dimm_config()
503 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); in get_dimm_config()
504 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); in get_dimm_config()
505 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); in get_dimm_config()
[all …]
|
| D | amd64_edac.h | 147 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) argument
148 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) argument
149 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) argument
152 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) argument
153 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) argument
154 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) argument
157 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) argument
178 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
179 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) argument
201 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) argument
[all …]
|
| D | i7300_edac.c | 353 struct i7300_pvt *pvt; in i7300_process_error_global() local
359 pvt = mci->pvt_info; in i7300_process_error_global()
362 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
372 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
378 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
388 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, in i7300_process_error_global()
408 struct i7300_pvt *pvt; in i7300_process_fbd_error() local
418 pvt = mci->pvt_info; in i7300_process_fbd_error()
421 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, in i7300_process_fbd_error()
430 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, in i7300_process_fbd_error()
[all …]
|
| D | i5000_edac.c | 388 struct i5000_pvt *pvt; in i5000_get_error_info() local
391 pvt = mci->pvt_info; in i5000_get_error_info()
394 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5000_get_error_info()
406 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
408 pci_read_config_word(pvt->branchmap_werrors, in i5000_get_error_info()
410 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
414 pci_write_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
424 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5000_get_error_info()
432 pci_read_config_dword(pvt->branchmap_werrors, in i5000_get_error_info()
434 pci_read_config_word(pvt->branchmap_werrors, in i5000_get_error_info()
[all …]
|
| D | i5400_edac.c | 438 struct i5400_pvt *pvt; in i5400_get_error_info() local
441 pvt = mci->pvt_info; in i5400_get_error_info()
444 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5400_get_error_info()
457 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
459 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
461 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
465 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
475 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5400_get_error_info()
483 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
485 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
[all …]
|
| D | amd64_edac_inj.c | 9 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_section_show() local
10 return sprintf(buf, "0x%x\n", pvt->injection.section); in amd64_inject_section_show()
24 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_section_store() local
37 pvt->injection.section = (u32) value; in amd64_inject_section_store()
46 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_word_show() local
47 return sprintf(buf, "0x%x\n", pvt->injection.word); in amd64_inject_word_show()
61 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_word_store() local
74 pvt->injection.word = (u32) value; in amd64_inject_word_store()
83 struct amd64_pvt *pvt = mci->pvt_info; in amd64_inject_ecc_vector_show() local
84 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in amd64_inject_ecc_vector_show()
[all …]
|
| D | e752x_edac.c | 308 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; in ctl_page_to_phys() local
312 if (page < pvt->tolm) in ctl_page_to_phys()
315 if ((page >= 0x100000) && (page < pvt->remapbase)) in ctl_page_to_phys()
318 remap = (page - pvt->tolm) + pvt->remapbase; in ctl_page_to_phys()
320 if (remap < pvt->remaplimit) in ctl_page_to_phys()
324 return pvt->tolm - 1; in ctl_page_to_phys()
334 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; in do_process_ce() local
342 if (pvt->mc_symmetric) { in do_process_ce()
347 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], in do_process_ce()
348 pvt->map[4], pvt->map[5], pvt->map[6], in do_process_ce()
[all …]
|
| D | e7xxx_edac.c | 186 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; in ctl_page_to_phys() local
190 if ((page < pvt->tolm) || in ctl_page_to_phys()
191 ((page >= 0x100000) && (page < pvt->remapbase))) in ctl_page_to_phys()
194 remap = (page - pvt->tolm) + pvt->remapbase; in ctl_page_to_phys()
196 if (remap < pvt->remaplimit) in ctl_page_to_phys()
200 return pvt->tolm - 1; in ctl_page_to_phys()
259 struct e7xxx_pvt *pvt; in e7xxx_get_error_info() local
261 pvt = (struct e7xxx_pvt *)mci->pvt_info; in e7xxx_get_error_info()
262 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); in e7xxx_get_error_info()
263 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); in e7xxx_get_error_info()
[all …]
|
| D | octeon_edac-lmc.c | 73 struct octeon_lmc_pvt *pvt = mci->pvt_info; in octeon_lmc_edac_poll_o2() local
78 if (!pvt->inject) in octeon_lmc_edac_poll_o2()
82 if (pvt->error_type == 1) in octeon_lmc_edac_poll_o2()
84 if (pvt->error_type == 2) in octeon_lmc_edac_poll_o2()
90 if (likely(!pvt->inject)) in octeon_lmc_edac_poll_o2()
93 fadr.cn61xx.fdimm = pvt->dimm; in octeon_lmc_edac_poll_o2()
94 fadr.cn61xx.fbunk = pvt->rank; in octeon_lmc_edac_poll_o2()
95 fadr.cn61xx.fbank = pvt->bank; in octeon_lmc_edac_poll_o2()
96 fadr.cn61xx.frow = pvt->row; in octeon_lmc_edac_poll_o2()
97 fadr.cn61xx.fcol = pvt->col; in octeon_lmc_edac_poll_o2()
[all …]
|