| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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| D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra210-ahub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
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| D | nvidia,tegra186-dspk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^dspk@[0-9a-f]*$"
26 - const: nvidia,tegra186-dspk
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| D | nvidia,tegra210-dmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^dmic@[0-9a-f]*$"
25 - const: nvidia,tegra210-dmic
26 - items:
27 - enum:
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| D | nvidia,tegra210-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Inter-IC Sound (I2S) controller implements full-duplex,
11 bi-directional and single direction point-to-point serial
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^i2s@[0-9a-f]*$"
25 - const: nvidia,tegra210-i2s
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| D | brcm,cygnus-audio.txt | 4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-conf.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
21 "#clock-cells"); in __set_clk_parents()
22 if (num_parents == -EINVAL) in __set_clk_parents()
23 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
28 "#clock-cells", index, &clkspec); in __set_clk_parents()
31 if (rc == -ENOENT) in __set_clk_parents()
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| /kernel/linux/linux-4.19/drivers/clk/ |
| D | clk-conf.c | 11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
23 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
24 "#clock-cells"); in __set_clk_parents()
25 if (num_parents == -EINVAL) in __set_clk_parents()
26 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
30 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
31 "#clock-cells", index, &clkspec); in __set_clk_parents()
34 if (rc == -ENOENT) in __set_clk_parents()
43 if (PTR_ERR(pclk) != -EPROBE_DEFER) in __set_clk_parents()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
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| D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.txt | 1 STM32 Real Time Clock
4 - compatible: can be one of the following:
5 - "st,stm32-rtc" for devices compatible with stm32(f4/f7).
6 - "st,stm32h7-rtc" for devices compatible with stm32h7.
7 - "st,stm32mp1-rtc" for devices compatible with stm32mp1.
8 - reg: address range of rtc register set.
9 - clocks: can use up to two clocks, depending on part used:
10 - "rtc_ck": RTC clock source.
11 - "pclk": RTC APB interface clock.
14 - clock-names: must be "rtc_ck" and "pclk".
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Real Time Clock Bindings
10 - Gabriel Fernandez <gabriel.fernandez@st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
26 clock-names:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/ |
| D | ti,j721e-ufs.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
23 description: phandle to the M-PHY clock
25 power-domains:
28 assigned-clocks:
31 assigned-clock-parents:
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
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| D | exynos5422-odroidxu3-audio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/sound/samsung-i2s.h>
15 compatible = "samsung,odroid-xu3-audio";
16 model = "Odroid-XU3";
18 samsung,audio-widgets =
21 samsung,audio-routing =
29 assigned-clocks = <&clock CLK_MOUT_EPLL>,
30 <&clock CLK_MOUT_MAU_EPLL>,
31 <&clock CLK_MOUT_USER_MAU_EPLL>,
38 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
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| D | exynos5422-odroidxu4.dts | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd.
11 /dts-v1/;
12 #include <dt-bindings/sound/samsung-i2s.h>
13 #include "exynos5422-odroidxu3-common.dtsi"
17 compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \
21 compatible = "pwm-leds";
26 pwm-names = "pwm2";
28 linux,default-trigger = "heartbeat";
33 compatible = "samsung,odroid-xu3-audio";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 4 - compatible: should be one of the following.
5 - mediatek,mt2712-spi-slave: for mt2712 platforms
6 - reg: Address and length of the register set for the device.
7 - interrupts: Should contain spi interrupt.
8 - clocks: phandles to input clocks.
9 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
10 - clock-names: should be "spi" for the clock gate.
13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/ |
| D | brcm,cygnus-audio.txt | 4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | sp810.txt | 2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
27 - assigned-clocks: from the common clock binding;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | sp810.txt | 2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
27 - assigned-clocks: from the common clock binding;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sprd.txt | 6 - compatible : Should be "sprd,ums512-pwm".
7 - reg: Physical base address and length of the controller's registers.
8 - clocks: The phandle and specifier referencing the controller's clocks.
9 - clock-names: Should contain following entries:
10 "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11 "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
21 compatible = "sprd,ums512-pwm";
[all …]
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