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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/msm/
Ddpu.txt6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
23 - interrupts: interrupt signal from MDSS.
24 - interrupt-controller: identifies the node as an interrupt controller.
25 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddpu.txt6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
23 - interrupts: interrupt signal from MDSS.
24 - interrupt-controller: identifies the node as an interrupt controller.
25 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^dspk@[0-9a-f]*$"
26 - const: nvidia,tegra186-dspk
[all …]
Dnvidia,tegra210-dmic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^dmic@[0-9a-f]*$"
25 - const: nvidia,tegra210-dmic
26 - items:
27 - enum:
[all …]
Dbrcm,cygnus-audio.txt4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
Dnvidia,tegra210-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Inter-IC Sound (I2S) controller implements full-duplex,
11 bi-directional and single direction point-to-point serial
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^i2s@[0-9a-f]*$"
25 - const: nvidia,tegra210-i2s
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/img/
Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/kernel/linux/linux-4.19/arch/mips/boot/dts/img/
Dpistachio.dtsi10 #include <dt-bindings/clock/pistachio-clk.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/mips-gic.h>
14 #include <dt-bindings/reset/pistachio-resets.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
22 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
16 "clk_ade_core" for the ADE core clock.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
16 "clk_ade_core" for the ADE core clock.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-conf.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
21 "#clock-cells"); in __set_clk_parents()
22 if (num_parents == -EINVAL) in __set_clk_parents()
23 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
28 "#clock-cells", index, &clkspec); in __set_clk_parents()
31 if (rc == -ENOENT) in __set_clk_parents()
[all …]
/kernel/linux/linux-4.19/drivers/clk/
Dclk-conf.c11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
23 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
24 "#clock-cells"); in __set_clk_parents()
25 if (num_parents == -EINVAL) in __set_clk_parents()
26 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
30 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
31 "#clock-cells", index, &clkspec); in __set_clk_parents()
34 if (rc == -ENOENT) in __set_clk_parents()
43 if (PTR_ERR(pclk) != -EPROBE_DEFER) in __set_clk_parents()
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
[all …]
Dexynos5422-odroidxu3-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/sound/samsung-i2s.h>
15 compatible = "samsung,odroid-xu3-audio";
16 model = "Odroid-XU3";
18 samsung,audio-widgets =
21 samsung,audio-routing =
29 assigned-clocks = <&clock CLK_MOUT_EPLL>,
30 <&clock CLK_MOUT_MAU_EPLL>,
31 <&clock CLK_MOUT_USER_MAU_EPLL>,
38 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
[all …]
Dexynos5422-odroidxu4.dts1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd.
11 /dts-v1/;
12 #include <dt-bindings/sound/samsung-i2s.h>
13 #include "exynos5422-odroidxu3-common.dtsi"
17 compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \
21 compatible = "pwm-leds";
26 pwm-names = "pwm2";
28 linux,default-trigger = "heartbeat";
33 compatible = "samsung,odroid-xu3-audio";
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dvf610-nfc.txt7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
16 clock are found in the SoC hardware reference manual. Furthermore,
17 there might be restrictions on maximum rates when using hardware ECC.
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Dvf610-nfc.txt7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
16 clock are found in the SoC hardware reference manual. Furthermore,
17 there might be restrictions on maximum rates when using hardware ECC.
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
[all …]

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