| /kernel/linux/linux-4.19/drivers/pinctrl/sh-pfc/ |
| D | sh_pfc.h | 15 #include <linux/pinctrl/pinconf-generic.h>
38 const char *name; member
44 .name = #alias, \
52 const char *name; member
65 .name = #n#s, \
83 .name = #n, \
89 const char *name; member
96 const char *name; member
108 * - name: Register name (unused, for documentation purposes only)
109 * - r: Physical register address
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| /kernel/linux/linux-5.10/drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
39 const char *name; member
45 .name = #alias, \
54 const char *name; member
68 .name = #n#s#__VA_ARGS__, \
99 .name = #n, \
105 const char *name; member
112 const char *name; member
132 * - name: Register name (unused, for documentation purposes only)
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| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
30 #include <dt-bindings/pinctrl/samsung.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| D | pinctrl-samsung.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
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| D | pinctrl-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 .name = id \
112 .eint_mask = (1 << (pins)) - 1, \
114 .name = id \
126 .name = id \
136 .eint_mask = (1 << (pins)) - 1, \
138 .name = id \
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| /kernel/linux/linux-4.19/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
30 #include <dt-bindings/pinctrl/samsung.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| D | pinctrl-samsung.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
[all …]
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| D | pinctrl-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 .name = id \
112 .eint_mask = (1 << (pins)) - 1, \
114 .name = id \
126 .name = id \
136 .eint_mask = (1 << (pins)) - 1, \
138 .name = id \
[all …]
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| /kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/ |
| D | adf_transport_debug.c | 1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
15 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
21 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
22 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
25 return ring->base_addr + in adf_ring_start()
26 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
31 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
33 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
34 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
[all …]
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| /kernel/linux/linux-4.19/drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 7 * With some ideas taken from pinctrl-samsung:
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
37 #include <linux/pinctrl/pinconf-generic.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
84 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * @offset: if initialized to -1 it will be autocalculated, by specifying
128 * @reg_base: register base of the gpio bank
130 * @clk: clock of the gpio bank
131 * @irq: interrupt of the gpio bank
[all …]
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| D | pinctrl-st.c | 62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
98 * (direction, retime-type, retime-clk, retime-delay)
100 * +----------------+
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
104 * +----------------+ v
106 * +----------------+ ^
108 * +----------------+-------------
109 *[24] | reserved-2 |
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| /kernel/linux/linux-4.19/drivers/crypto/qat/qat_common/ |
| D | adf_transport_debug.c | 17 qat-linux@intel.com
31 * Neither the name of Intel Corporation nor the names of its
59 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
65 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
66 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
69 return ring->base_addr + in adf_ring_start()
70 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
75 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
77 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
78 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
[all …]
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| /kernel/linux/linux-4.19/drivers/pinctrl/stm32/ |
| D | pinctrl-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
33 #include "pinctrl-stm32.h"
64 const char *name; member
121 return function - 1; in stm32_gpio_get_alt()
131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
137 clk_enable(bank->clk); in __stm32_gpio_set()
139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
141 clk_disable(bank->clk); in __stm32_gpio_set()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-equilibrium.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
[all …]
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| D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
79 * @offset: if initialized to -1 it will be autocalculated, by specifying
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
125 * @reg_base: register base of the gpio bank
127 * @clk: clock of the gpio bank
[all …]
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| D | pinctrl-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
60 * There are two registers cfg0 and cfg1 in this style for each bank.
61 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
96 * (direction, retime-type, retime-clk, retime-delay)
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
102 * +----------------+ v
104 * +----------------+ ^
106 * +----------------+-------------
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| /kernel/linux/linux-4.19/drivers/pinctrl/sunxi/ |
| D | pinctrl-sunxi.h | 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
96 const char *name; member
119 const char *name; member
125 const char *name; member
163 .name = _name, \
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| /kernel/linux/linux-5.10/drivers/pinctrl/sunxi/ |
| D | pinctrl-sunxi.h | 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
118 const char *name; member
142 const char *name; member
148 const char *name; member
192 .name = _name, \
[all …]
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| /kernel/linux/linux-4.19/drivers/uio/ |
| D | uio_fsl_elbc_gpcm.c | 1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
[all …]
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/mce/ |
| D | amd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
75 const char *name; /* Short name for sysfs */ member
76 const char *long_name; /* Long name for pretty-printing */
108 return smca_names[t].name; in smca_get_name()
120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
128 if (!b->hwid) in smca_get_bank_type()
[all …]
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| /kernel/linux/linux-4.19/arch/x86/kernel/cpu/mcheck/ |
| D | mce_amd.c | 2 * (c) 2005-2016 Advanced Micro Devices, Inc.
7 * Written by Jacob Shin - AMD, Inc.
32 #include "mce-internal.h"
77 const char *name; /* Short name for sysfs */ member
78 const char *long_name; /* Long name for pretty-printing */
100 [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 }
108 return smca_names[t].name; in smca_get_name()
120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
[all …]
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| /kernel/linux/linux-5.10/drivers/uio/ |
| D | uio_fsl_elbc_gpcm.c | 1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | powerdomain.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
65 static struct powerdomain *_pwrdm_lookup(const char *name) in _pwrdm_lookup() argument
72 if (!strcmp(name, temp_pwrdm->name)) { in _pwrdm_lookup()
82 * _pwrdm_register - register a powerdomain
86 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
87 * already registered by the provided name, or 0 upon success.
94 if (!pwrdm || !pwrdm->name) in _pwrdm_register()
95 return -EINVAL; in _pwrdm_register()
[all …]
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