| /kernel/linux/linux-4.19/tools/testing/selftests/rseq/ |
| D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
45 static __thread __attribute__((tls_model("initial-exec")))
50 static __thread __attribute__((tls_model("initial-exec"), unused))
114 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
205 "addiu " INJECT_ASM_REG ", -1\n\t" \
223 if (loc_nr_loops == -1 && opt_modulo) { \
224 if (yield_mod_cnt == opt_modulo - 1) { \
299 intptr_t offset; member
316 intptr_t offset; member
325 /* A simple percpu spinlock. Grabs lock on current cpu. */
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| /kernel/linux/linux-5.10/tools/testing/selftests/rseq/ |
| D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
47 static __thread __attribute__((tls_model("initial-exec")))
52 static __thread __attribute__((tls_model("initial-exec"), unused))
116 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
207 "addiu " INJECT_ASM_REG ", -1\n\t" \
225 if (loc_nr_loops == -1 && opt_modulo) { \
226 if (yield_mod_cnt == opt_modulo - 1) { \
301 intptr_t offset; member
318 intptr_t offset; member
327 /* A simple percpu spinlock. Grabs lock on current cpu. */
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| /kernel/linux/linux-5.10/arch/arm/mach-zynq/ |
| D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
[all …]
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
66 ------------------------------------
[all …]
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| /kernel/linux/linux-4.19/Documentation/ |
| D | this_cpu_ops.txt | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
66 ------------------------------------
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-mvebu.c | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
[all …]
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| /kernel/linux/linux-4.19/drivers/gpio/ |
| D | gpio-mvebu.c | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-zynq/ |
| D | slcr.c | 4 * Copyright (c) 2011-2013 Xilinx Inc.
28 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
43 * zynq_slcr_write - Write to a register in SLCR block
46 * @offset: Register offset in SLCR block
50 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
52 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
56 * zynq_slcr_read - Read a register in SLCR block
59 * @offset: Register offset in SLCR block
63 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
65 return regmap_read(zynq_slcr_regmap, offset, val); in zynq_slcr_read()
[all …]
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| /kernel/linux/linux-4.19/arch/x86/include/asm/uv/ |
| D | uv_hub.h | 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
31 * M - The low M bits of a physical address represent the offset
36 * N - Number of bits in the node portion of a socket physical
39 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
42 * right shift the NASID by 1 to exclude the always-zero bit.
45 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
48 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
51 * GPA - (global physical address) a socket physical address converted
60 * +--------------------------------+---------------------+
62 * +--------------------------------+---------------------+
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| /kernel/linux/linux-4.19/arch/ia64/include/asm/uv/ |
| D | uv_hub.h | 23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
[all …]
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| /kernel/linux/linux-5.10/arch/ia64/include/asm/uv/ |
| D | uv_hub.h | 23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
[all …]
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| /kernel/linux/linux-5.10/arch/x86/include/asm/uv/ |
| D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
22 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
37 cpu = map + offset_in_page(offset); in cpu_set()
40 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
42 *cpu = v; in cpu_set()
45 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
|
| /kernel/linux/linux-5.10/kernel/time/ |
| D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
62 print_name_offset(m, timer->function); in print_timer()
63 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
65 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
68 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
69 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
86 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
[all …]
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| /kernel/linux/linux-4.19/kernel/time/ |
| D | timer_list.c | 23 #include "tick-internal.h"
26 int cpu; member
33 * to the console (on SysRq-Q):
67 print_name_offset(m, timer->function); in print_timer()
68 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
70 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
73 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
74 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
91 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
93 curr = timerqueue_getnext(&base->active); in print_active_timers()
[all …]
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| /kernel/linux/linux-4.19/tools/testing/selftests/vm/ |
| D | userfaultfd.c | 7 * the COPYING file in the top-level directory.
13 * There are three threads running per CPU:
15 * 1) one per-CPU thread takes a per-page pthread_mutex in a random
17 * area_src), and increments a per-page counter in the same page,
20 * 2) another per-CPU thread handles the userfaults generated by
24 * 3) one last per-CPU thread transfers the memory in the background
26 * 2). Each cpu thread takes cares of transferring a portion of the
34 * per-CPU threads 1 by triggering userfaults inside
47 * # 10MiB-~6GiB 999 bounces, continue forever unless an error triggers
103 /* pthread_mutex_t starts at page offset 0 */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | krait-cc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
42 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
44 mux->reparent = false; in krait_notifier_cb()
51 if (!mux->reparent) in krait_notifier_cb()
52 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
53 mux->old_index); in krait_notifier_cb()
64 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/lima/ |
| D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-hisi/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-hisi/ |
| D | platsmp.c | 4 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
26 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
28 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
29 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
31 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
34 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
36 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
37 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
39 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
62 u32 offset = 0; in hi3xxx_smp_prepare_cpus() local
[all …]
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| /kernel/linux/linux-4.19/drivers/oprofile/ |
| D | buffer_sync.c | 4 * @remark Copyright 2002-2009 OProfile authors
12 * CPU buffer is processed and entered into the
17 * transitory EIP value into a persistent dentry/offset
20 * See fs/dcookies.c for a description of the dentry/offset
62 list_add(&task->tasks, &dying_tasks); in task_free_notify()
74 /* To avoid latency problems, we only process the current CPU, in task_exit_notify()
75 * hoping that most samples for the task are on this CPU in task_exit_notify()
91 struct mm_struct *mm = current->mm; in munmap_notify()
94 down_read(&mm->mmap_sem); in munmap_notify()
97 if (mpnt && mpnt->vm_file && (mpnt->vm_flags & VM_EXEC)) { in munmap_notify()
[all …]
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| /kernel/liteos_a/arch/arm/gic/ |
| D | gic_v3.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
45 return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) | /* 3: Serial number, 32: Register bit offset */ in MpidrToAffinity()
46 (MPIDR_AFF_LEVEL(mpidr, 2) << 16) | /* 2: Serial number, 16: Register bit offset */ in MpidrToAffinity()
47 (MPIDR_AFF_LEVEL(mpidr, 1) << 8) | /* 1: Serial number, 8: Register bit offset */ in MpidrToAffinity()
53 STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask) in NextCpu() argument
55 UINT32 next = cpu + 1; in NextCpu()
73 UINT32 cpu = *base; in GicTargetList() local
74 UINT64 mpidr = CPU_MAP_GET(cpu); in GicTargetList()
75 while (cpu < LOSCFG_KERNEL_CORE_NUM) { in GicTargetList()
[all …]
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| /kernel/linux/linux-5.10/drivers/oprofile/ |
| D | buffer_sync.c | 4 * @remark Copyright 2002-2009 OProfile authors
12 * CPU buffer is processed and entered into the
17 * transitory EIP value into a persistent dentry/offset
20 * See fs/dcookies.c for a description of the dentry/offset
62 list_add(&task->tasks, &dying_tasks); in task_free_notify()
74 /* To avoid latency problems, we only process the current CPU, in task_exit_notify()
75 * hoping that most samples for the task are on this CPU in task_exit_notify()
91 struct mm_struct *mm = current->mm; in munmap_notify()
97 if (mpnt && mpnt->vm_file && (mpnt->vm_flags & VM_EXEC)) { in munmap_notify()
99 /* To avoid latency problems, we only process the current CPU, in munmap_notify()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | qcom,msm-timer.txt | 5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | qcom,msm-timer.txt | 5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
[all …]
|