| /kernel/linux/linux-5.10/drivers/misc/habanalabs/common/ |
| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
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| /kernel/linux/linux-4.19/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
33 * Lockless access is OK, because file->private data is set in fuse_get_dev()
36 return READ_ONCE(file->private_data); in fuse_get_dev()
46 INIT_LIST_HEAD(&req->list); in fuse_request_init()
47 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
48 init_waitqueue_head(&req->waitq); in fuse_request_init()
49 refcount_set(&req->count, 1); in fuse_request_init()
50 req->pages = pages; in fuse_request_init()
51 req->page_descs = page_descs; in fuse_request_init()
52 req->max_pages = npages; in fuse_request_init()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/ |
| D | i915_perf.c | 2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
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| D | i915_request.c | 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
73 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
75 return -ENOMEM; in igt_add_request()
87 int err = -EINVAL; in igt_wait_request()
91 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
93 return -ENOMEM; in igt_wait_request()
97 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
102 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
114 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
124 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
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| /kernel/linux/linux-4.19/drivers/spi/ |
| D | spi-omap2-mcspi.c | 24 #include <linux/dma-mapping.h>
40 #include <linux/platform_data/spi-omap2-mcspi.h>
57 /* per-channel banks, 0x14 bytes each, first is: */
64 /* per-register bitmasks: */
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
125 struct list_head cs; member
156 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
163 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
169 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
171 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
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| D | spi-orion.c | 5 * Copyright (C) 2007-2008 Marvell Ltd.
67 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ argument
79 * have both is for managing the armada-370-spi case with old
111 return orion_spi->base + reg; in spi_reg()
145 orion_spi = spi_master_get_devdata(spi->master); in orion_spi_baudrate_set()
146 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
148 tclk_hz = clk_get_rate(orion_spi->clk); in orion_spi_baudrate_set()
150 if (devdata->typ == ARMADA_SPI) { in orion_spi_baudrate_set()
178 sppr = fls(divider) - 4; in orion_spi_baudrate_set()
185 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; in orion_spi_baudrate_set()
[all …]
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| /kernel/linux/linux-5.10/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | selftest_engine_cs.c | 2 * SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(>->rps.num_waiters); in perf_begin()
30 schedule_work(>->rps.work); in perf_begin()
31 flush_work(>->rps.work); in perf_begin()
36 atomic_dec(>->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 u32 *cs; in write_timestamp() local
47 cs = intel_ring_begin(rq, 4); in write_timestamp()
48 if (IS_ERR(cs)) in write_timestamp()
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| D | selftest_lrc.c | 2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
116 engine->name, in wait_for_reset()
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| D | selftest_ring_submission.c | 1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (INTEL_GEN(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
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| D | selftest_rc6.c | 2 * SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = >->rc6; in live_rc6_manual()
46 if (!rc6->enabled) in live_rc6_manual()
50 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
64 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
67 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
69 (res[1] - res[0]) >> 10); in live_rc6_manual()
70 err = -EINVAL; in live_rc6_manual()
77 err = -EINVAL; in live_rc6_manual()
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| D | intel_ring_submission.c | 2 * Copyright © 2008-2010 Intel Corporation
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
44 * set-context and then emitting the batch.
54 if (engine->class == RENDER_CLASS) { in set_hwstam()
55 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
69 if (INTEL_GEN(engine->i915) >= 4) in set_hws_pga()
72 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
80 return sg_page(obj->mm.pages->sgl); in status_page()
97 if (IS_GEN(engine->i915, 7)) { in set_hwsp()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/i915/selftests/ |
| D | intel_workarounds.c | 2 * SPDX-License-Identifier: MIT
18 const u32 base = engine->mmio_base; in read_nonprivs()
19 u32 srm, *cs; in read_nonprivs() local
23 result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); in read_nonprivs()
29 cs = i915_gem_object_pin_map(result, I915_MAP_WB); in read_nonprivs()
30 if (IS_ERR(cs)) { in read_nonprivs()
31 err = PTR_ERR(cs); in read_nonprivs()
34 memset(cs, 0xc5, PAGE_SIZE); in read_nonprivs()
37 vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL); in read_nonprivs()
58 if (INTEL_GEN(ctx->i915) >= 8) in read_nonprivs()
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/kpc2000/ |
| D | kpc2000_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
126 unsigned int cs : 4; /* Chip Select */ member
163 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx) in kp_spi_read_reg() argument
165 u64 __iomem *addr = cs->base; in kp_spi_read_reg()
168 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)) in kp_spi_read_reg()
169 return cs->conf_cache; in kp_spi_read_reg()
175 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val) in kp_spi_write_reg() argument
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| /kernel/linux/linux-4.19/drivers/isdn/gigaset/ |
| D | common.c | 41 * gigaset_dbg_buffer() - dump data in ASCII and hex for debugging
56 size_t space = sizeof outbuf - 1; in gigaset_dbg_buffer()
57 unsigned char *out = outbuf; in gigaset_dbg_buffer() local
60 while (numin--) { in gigaset_dbg_buffer()
63 if (!space--) in gigaset_dbg_buffer()
65 *out++ = '\\'; in gigaset_dbg_buffer()
68 if (!space--) in gigaset_dbg_buffer()
70 *out++ = '~'; in gigaset_dbg_buffer()
74 if (!space--) in gigaset_dbg_buffer()
76 *out++ = '^'; in gigaset_dbg_buffer()
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| D | interface.c | 21 static int if_lock(struct cardstate *cs, int *arg) in if_lock() argument
25 gig_dbg(DEBUG_IF, "%u: if_lock (%d)", cs->minor_index, cmd); in if_lock()
28 return -EINVAL; in if_lock()
31 *arg = cs->mstate == MS_LOCKED; in if_lock()
35 if (!cmd && cs->mstate == MS_LOCKED && cs->connected) { in if_lock()
36 cs->ops->set_modem_ctrl(cs, 0, TIOCM_DTR | TIOCM_RTS); in if_lock()
37 cs->ops->baud_rate(cs, B115200); in if_lock()
38 cs->ops->set_line_ctrl(cs, CS8); in if_lock()
39 cs->control_state = TIOCM_DTR | TIOCM_RTS; in if_lock()
42 cs->waiting = 1; in if_lock()
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| D | capi.c | 76 /* values for bcs->apconnstate */
112 [1] = { "8090A3", NULL }, /* Speech (A-law) */
115 [4] = { "9090A3", NULL }, /* 3,1 kHz audio (A-law) */
151 static inline void ignore_cstruct_param(struct cardstate *cs, _cstruct param, in ignore_cstruct_param() argument
155 dev_warn(cs->dev, "%s: ignoring unsupported parameter: %s\n", in ignore_cstruct_param()
162 * return value: result length, -1 on error
164 static int encode_ie(char *in, u8 *out, int maxlen) in encode_ie() argument
169 return -1; in encode_ie()
170 out[++l] = (hex_to_bin(in[0]) << 4) + hex_to_bin(in[1]); in encode_ie()
173 out[0] = l; in encode_ie()
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| /kernel/linux/linux-5.10/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
59 #include <linux/backing-dev.h>
89 * The user-configured masks can only be changed by writing to
103 * The user-configured masks are always the same with effective masks.
106 /* user-configured CPUs and Memory Nodes allow to tasks */
116 * CPUs allocated to child sub-partitions (default hierarchy only)
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| /kernel/linux/linux-4.19/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
57 #include <linux/backing-dev.h>
87 * The user-configured masks can only be changed by writing to
101 * The user-configured masks are always the same with effective masks.
104 /* user-configured CPUs and Memory Nodes allow to tasks */
115 * - top_cpuset.old_mems_allowed is initialized to mems_allowed.
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| /kernel/linux/linux-4.19/drivers/gpu/drm/i915/ |
| D | intel_ringbuffer.c | 2 * Copyright © 2008-2010 Intel Corporation
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
42 * set-context and then emitting the batch.
56 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
63 space = __intel_ring_space(ring->head, ring->emit, ring->size); in intel_ring_update_space()
65 ring->space = space; in intel_ring_update_space()
72 u32 cmd, *cs; in gen2_render_ring_flush() local
79 cs = intel_ring_begin(rq, 2); in gen2_render_ring_flush()
80 if (IS_ERR(cs)) in gen2_render_ring_flush()
81 return PTR_ERR(cs); in gen2_render_ring_flush()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
163 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
174 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
198 u32 *cs; in restore_context_mmio_for_inhibit() local
201 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
202 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
42 * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
195 u32 *cs; in restore_context_mmio_for_inhibit() local
198 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
199 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
200 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
205 ret = req->engine->emit_flush(req, EMIT_BARRIER); in restore_context_mmio_for_inhibit()
209 cs = intel_ring_begin(req, count * 2 + 2); in restore_context_mmio_for_inhibit()
210 if (IS_ERR(cs)) in restore_context_mmio_for_inhibit()
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| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | jade_irq.c | 14 waitforCEC(struct IsdnCardState *cs, int jade, int reg) in waitforCEC() argument
18 while ((READJADE(cs, jade, jade_HDLC_STAR) & mask) && to) { in waitforCEC()
20 to--; in waitforCEC()
28 waitforXFW(struct IsdnCardState *cs, int jade) in waitforXFW() argument
34 WriteJADECMDR(struct IsdnCardState *cs, int jade, int reg, u_char data) in WriteJADECMDR() argument
36 waitforCEC(cs, jade, reg); in WriteJADECMDR()
37 WRITEJADE(cs, jade, reg, data); in WriteJADECMDR()
46 struct IsdnCardState *cs = bcs->cs; in jade_empty_fifo() local
48 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in jade_empty_fifo()
49 debugl1(cs, "jade_empty_fifo"); in jade_empty_fifo()
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| D | hscx_irq.c | 3 * low level b-channel stuff for Siemens HSCX
17 waitforCEC(struct IsdnCardState *cs, int hscx) in waitforCEC() argument
21 while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { in waitforCEC()
23 to--; in waitforCEC()
31 waitforXFW(struct IsdnCardState *cs, int hscx) in waitforXFW() argument
35 while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { in waitforXFW()
37 to--; in waitforXFW()
44 WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) in WriteHSCXCMDR() argument
46 waitforCEC(cs, hscx); in WriteHSCXCMDR()
47 WRITEHSCX(cs, hscx, HSCX_CMDR, data); in WriteHSCXCMDR()
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