| /kernel/linux/linux-4.19/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 2 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
15 #include <linux/clk-provider.h>
35 #define PRG_ETH0_EXT_RMII_MODE 4
38 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
39 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
58 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
78 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
83 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
87 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
90 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk() argument
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| D | dwmac-sti.c | 2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
48 * ------------------------------------------------
51 * ------------------------------------------------
53 *| | clk-125/txclk | txclk |
54 * ------------------------------------------------
56 *| | clk-125/txclk | clkgen |
58 * ------------------------------------------------
60 *| | |clkgen/phyclk-in |
61 * ------------------------------------------------
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| D | dwmac-oxnas.c | 2 * Oxford Semiconductor OXNAS DWMAC glue layer
41 #define DWMAC_LOW_TX_SOURCE 4
65 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
70 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
74 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
78 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
80 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
97 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
100 value = DWMAC_TX_VARDELAY(4) | in oxnas_dwmac_init()
104 regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value); in oxnas_dwmac_init()
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| D | dwmac-anarion.c | 2 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl((void *)(gmac->ctl_block + reg)); in gmac_read_reg()
34 writel(val, (void *)(gmac->ctl_block + reg)); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
70 ctl_block = devm_ioremap_resource(&pdev->dev, res); in anarion_config_dt()
72 dev_err(&pdev->dev, "Cannot get reset region (%ld)!\n", in anarion_config_dt()
77 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
79 return ERR_PTR(-ENOMEM); in anarion_config_dt()
81 gmac->ctl_block = (uintptr_t)ctl_block; in anarion_config_dt()
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| D | dwmac-sun8i.c | 2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
20 #include <linux/mdio-mux.h>
35 /* General notes on dwmac-sun8i:
40 /* struct emac_variant - Describe dwmac-sun8i hardware variant
68 /* struct sunxi_priv_data - hold all sunxi private data
76 * @mux_handle: Internal pointer used by mdio-mux lib
190 #define EMAC_RX_TH_MASK GENMASK(4, 5)
192 #define EMAC_RX_TH_64 (0x1 << 4)
193 #define EMAC_RX_TH_96 (0x2 << 4)
194 #define EMAC_RX_TH_128 (0x3 << 4)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
30 #define PRG_ETH0_EXT_RMII_MODE 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
74 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
96 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
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| D | dwmac-oxnas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Oxford Semiconductor OXNAS DWMAC glue layer
35 #define DWMAC_LOW_TX_SOURCE 4
59 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
64 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
68 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
72 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
74 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
91 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
94 value = DWMAC_TX_VARDELAY(4) | in oxnas_dwmac_init()
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| D | dwmac-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
44 * ------------------------------------------------
47 * ------------------------------------------------
49 *| | clk-125/txclk | txclk |
50 * ------------------------------------------------
52 *| | clk-125/txclk | clkgen |
54 * ------------------------------------------------
56 *| | |clkgen/phyclk-in |
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| D | dwmac-anarion.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl((void *)(gmac->ctl_block + reg)); in gmac_read_reg()
34 writel(val, (void *)(gmac->ctl_block + reg)); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
71 dev_err(&pdev->dev, "Cannot get reset region (%ld)!\n", in anarion_config_dt()
76 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
78 return ERR_PTR(-ENOMEM); in anarion_config_dt()
80 gmac->ctl_block = (uintptr_t)ctl_block; in anarion_config_dt()
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| D | dwmac-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * DWMAC Intel header file
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
19 #define SERDES_PWR_ST_SHIFT 4
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| D | dwmac-sun8i.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
59 /* struct sunxi_priv_data - hold all sunxi private data
68 * @mux_handle: Internal pointer used by mdio-mux lib
147 * co-packaged AC200 chip instead.
197 #define EMAC_RX_TH_MASK GENMASK(5, 4)
199 #define EMAC_RX_TH_64 (0x1 << 4)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer Device Tree Bindings
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
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| D | socfpga-dwmac.txt | 1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and any applicable more detailed
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | meson-dwmac.txt | 1 * Amlogic Meson DWMAC Ethernet controller
3 The device inherits all the properties of the dwmac/stmmac devices
9 - compatible: Depending on the platform this should be one of:
10 - "amlogic,meson6-dwmac"
11 - "amlogic,meson8b-dwmac"
12 - "amlogic,meson8m2-dwmac"
13 - "amlogic,meson-gxbb-dwmac"
14 - "amlogic,meson-axg-dwmac"
15 Additionally "snps,dwmac" and any applicable more
19 - reg: The first register range should be the one of the DWMAC
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| D | socfpga-dwmac.txt | 1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : Should contain "altr,socfpga-stmmac" along with
10 "snps,dwmac" and any applicable more detailed
12 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
14 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
18 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
19 DWMAC controller is connected emac splitter.
20 phy-mode: The phy mode the ethernet operates in
21 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
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| D | stmmac.txt | 4 - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" or
5 "snps,dwxgmac-<ip_version>", "snps,dwxgmac".
6 For backwards compatibility: "st,spear600-gmac" is also supported.
7 - reg: Address and length of the register set for the device
8 - interrupts: Should contain the STMMAC interrupts
9 - interrupt-names: Should contain a list of interrupt names corresponding to
12 - "macirq" (combined signal for various interrupt events)
13 - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)
14 - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state)
15 - phy-mode: See ethernet.txt file in the same directory.
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 17 /dts-v1/;
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53", "arm,armv8";
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| /kernel/linux/linux-4.19/Documentation/networking/ |
| D | stmmac.txt | 3 Copyright (C) 2007-2015 STMicroelectronics Ltd
6 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
22 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
43 4) Driver information and notes
50 net_device structure, enabling the scatter-gather feature. This is true on
62 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
63 buffers in order to avoid the memcpy (zero-copy).
68 New chips have an HW RX-Watchdog used for this mitigation.
80 and linked-list(CHAINED) mode. In RING each descriptor points to two
101 # ethtool -S ethX
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | socfpga_arria10.dtsi | 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | socfpga_arria10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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| /kernel/linux/linux-4.19/arch/arc/boot/dts/ |
| D | hsdk.dts | 12 /dts-v1/;
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 #address-cells = <1>;
34 #size-cells = <0>;
65 input_clk: input-clk {
66 #clock-cells = <0>;
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