| /kernel/linux/linux-4.19/drivers/gpu/drm/etnaviv/ |
| D | etnaviv_gpu.c | 29 { .name = "etnaviv-gpu,2d" },
37 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 *value = gpu->identity.model; in etnaviv_gpu_get_param()
45 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
49 *value = gpu->identity.features; in etnaviv_gpu_get_param()
53 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/ |
| D | etnaviv_gpu.c | 35 { .name = "etnaviv-gpu,2d" },
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/ |
| D | msm_gpu.c | 37 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_target() local
45 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
54 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_dev_status() local
59 status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status()
60 gpu->funcs->gpu_busy(gpu, &cycles); in msm_devfreq_get_dev_status()
62 status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq; in msm_devfreq_get_dev_status()
64 gpu->devfreq.busy_cycles = cycles; in msm_devfreq_get_dev_status()
67 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status()
68 gpu->devfreq.time = time; in msm_devfreq_get_dev_status()
75 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_cur_freq() local
[all …]
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| D | msm_gpu.h | 55 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
56 int (*hw_init)(struct msm_gpu *gpu);
57 int (*pm_suspend)(struct msm_gpu *gpu);
58 int (*pm_resume)(struct msm_gpu *gpu);
59 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
63 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 void (*recover)(struct msm_gpu *gpu);
65 void (*destroy)(struct msm_gpu *gpu);
67 /* show GPU status in debugfs: */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| D | msm_gpu.c | 27 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_target() local
37 if (gpu->funcs->gpu_set_freq) in msm_devfreq_target()
38 gpu->funcs->gpu_set_freq(gpu, opp); in msm_devfreq_target()
40 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
50 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_get_dev_status() local
53 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_dev_status()
54 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_dev_status()
56 status->current_frequency = clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status()
58 status->busy_time = gpu->funcs->gpu_busy(gpu); in msm_devfreq_get_dev_status()
61 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status()
[all …]
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| D | msm_gpu.h | 45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
56 /* show GPU status in debugfs: */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | a3xx_gpu.c | 28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
33 struct msm_drm_private *priv = gpu->dev->dev_private; in a3xx_submit()
70 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ in a3xx_submit()
83 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
86 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
88 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
109 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
110 return a3xx_idle(gpu); in a3xx_me_init()
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| D | a5xx_gpu.c | 17 static void a5xx_dump(struct msm_gpu *gpu);
21 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
24 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
54 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
57 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
59 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
104 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
105 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
111 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
113 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
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| D | a6xx_gpu.c | 15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
36 if (!adreno_idle(gpu, ring)) in a6xx_idle()
39 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
40 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a6xx_idle()
41 gpu->name, __builtin_return_address(0), in a6xx_idle()
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
[all …]
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| D | a4xx_gpu.c | 22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument
27 struct msm_drm_private *priv = gpu->dev->dev_private; in a4xx_submit()
64 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ in a4xx_submit()
70 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()
77 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
79 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
82 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
84 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
[all …]
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| D | a5xx_power.c | 103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
133 /* Hard code the A530 GPU thermal sensor ID for the GPMU */ in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
[all …]
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| D | adreno_gpu.h | 49 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
87 * of gpu firmware to linux-firmware, the fw files were
111 * GPU specific offsets will be exported by GPU specific
143 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) in adreno_is_a2xx() argument
145 return (gpu->revn < 300); in adreno_is_a2xx()
148 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) in adreno_is_a20x() argument
150 return (gpu->revn < 210); in adreno_is_a20x()
153 static inline bool adreno_is_a225(struct adreno_gpu *gpu) in adreno_is_a225() argument
155 return gpu->revn == 225; in adreno_is_a225()
158 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument
[all …]
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| D | a2xx_gpu.c | 10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
15 struct msm_drm_private *priv = gpu->dev->dev_private; in a2xx_submit()
52 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
55 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
98 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
99 return a2xx_idle(gpu); in a2xx_me_init()
102 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
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| D | a5xx_preempt.c | 25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
79 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
86 DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.c | 10 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
12 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
20 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
24 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
28 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
31 if (!adreno_idle(gpu, ring)) in a6xx_idle()
34 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
35 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a6xx_idle()
36 gpu->name, __builtin_return_address(0), in a6xx_idle()
37 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
[all …]
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| D | a3xx_gpu.c | 43 static void a3xx_dump(struct msm_gpu *gpu);
44 static bool a3xx_idle(struct msm_gpu *gpu);
46 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
48 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
69 gpu->funcs->flush(gpu, ring); in a3xx_me_init()
70 return a3xx_idle(gpu); in a3xx_me_init()
73 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
75 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
80 DBG("%s", gpu->name); in a3xx_hw_init()
84 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
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| D | a4xx_gpu.c | 34 static void a4xx_dump(struct msm_gpu *gpu);
35 static bool a4xx_idle(struct msm_gpu *gpu);
41 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
43 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
46 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
48 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
50 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
52 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
54 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
56 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
[all …]
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| D | a5xx_gpu.c | 30 static void a5xx_dump(struct msm_gpu *gpu);
34 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname) in zap_shader_load_mdt() argument
36 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
66 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
95 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { in zap_shader_load_mdt()
124 static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_flush() argument
126 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
146 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
149 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit, in a5xx_submit_in_rb() argument
152 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
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| D | a5xx_power.c | 100 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
102 struct drm_device *dev = gpu->dev; in _get_mvolts()
119 static void a5xx_lm_setup(struct msm_gpu *gpu) in a5xx_lm_setup() argument
121 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_lm_setup()
127 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a5xx_lm_setup()
130 /* Hard code the A530 GPU thermal sensor ID for the GPMU */ in a5xx_lm_setup()
131 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a5xx_lm_setup()
132 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a5xx_lm_setup()
133 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a5xx_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a5xx_lm_setup()
[all …]
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| D | adreno_gpu.h | 77 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
107 * of gpu firmware to linux-firmware, the fw files were
131 * GPU specific offsets will be exported by GPU specific
158 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) in adreno_is_a3xx() argument
160 return (gpu->revn >= 300) && (gpu->revn < 400); in adreno_is_a3xx()
163 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument
165 return gpu->revn == 305; in adreno_is_a305()
168 static inline bool adreno_is_a306(struct adreno_gpu *gpu) in adreno_is_a306() argument
171 return gpu->revn == 307; in adreno_is_a306()
174 static inline bool adreno_is_a320(struct adreno_gpu *gpu) in adreno_is_a320() argument
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| D | a5xx_preempt.c | 34 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
43 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
49 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
61 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
65 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
70 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
72 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
88 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
89 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
95 dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer()
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| /kernel/linux/linux-4.19/Documentation/gpu/ |
| D | i915.rst | 19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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| /kernel/linux/linux-5.10/Documentation/gpu/ |
| D | i915.rst | 19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | Kconfig | 184 GPU memory management subsystem for devices with multiple
185 GPU memory types. Will be enabled automatically if a device driver
235 source "drivers/gpu/drm/i2c/Kconfig"
237 source "drivers/gpu/drm/arm/Kconfig"
257 source "drivers/gpu/drm/radeon/Kconfig"
260 tristate "AMD GPU"
276 source "drivers/gpu/drm/amd/amdgpu/Kconfig"
278 source "drivers/gpu/drm/nouveau/Kconfig"
280 source "drivers/gpu/drm/i915/Kconfig"
298 running GPU in a headless machines. Choose this option to get
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| /kernel/linux/linux-4.19/drivers/gpu/drm/ |
| D | Kconfig | 159 GPU memory management subsystem for devices with multiple
160 GPU memory types. Will be enabled automatically if a device driver
188 source "drivers/gpu/drm/i2c/Kconfig"
190 source "drivers/gpu/drm/arm/Kconfig"
210 source "drivers/gpu/drm/radeon/Kconfig"
213 tristate "AMD GPU"
230 source "drivers/gpu/drm/amd/amdgpu/Kconfig"
232 source "drivers/gpu/drm/amd/lib/Kconfig"
234 source "drivers/gpu/drm/nouveau/Kconfig"
236 source "drivers/gpu/drm/i915/Kconfig"
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