| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/omap/ |
| D | crossbar.txt | 4 time, so they have to be muxed to the irq-controller appropriately.
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/ |
| D | crossbar.txt | 4 time, so they have to be muxed to the irq-controller appropriately.
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-crossbar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irqchip/irq-crossbar.c
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
16 #define IRQ_FREE -1
17 #define IRQ_RESERVED -2
18 #define IRQ_SKIP -3
22 * struct crossbar_device - crossbar device description
47 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writel()
52 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writew()
57 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writeb()
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| D | irq-nvic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
9 * ARMv7-M CPUs (Cortex-M3/M4)
33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
76 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
85 return -ENOMEM; in nvic_of_init()
88 irqs = numbanks * 32; in nvic_of_init()
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| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-crossbar.c | 2 * drivers/irqchip/irq-crossbar.c
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
20 #define IRQ_FREE -1
21 #define IRQ_RESERVED -2
22 #define IRQ_SKIP -3
26 * struct crossbar_device - crossbar device description
51 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writel()
56 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writew()
61 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writeb()
85 if (!irq_domain_get_of_node(domain->parent)) in allocate_gic_irq()
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| D | irq-nvic.c | 2 * drivers/irq/irq-nvic.c
4 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
12 * ARMv7-M CPUs (Cortex-M3/M4)
36 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
37 * 16 irqs.
39 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
55 if (WARN_ON(fwspec->param_count < 1)) in nvic_irq_domain_translate()
56 return -EINVAL; in nvic_irq_domain_translate()
57 *hwirq = fwspec->param[0]; in nvic_irq_domain_translate()
90 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
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| D | irq-s3c24xx.c | 4 * Copyright (c) 2003-2004 Simtec Electronics
37 #include <mach/regs-irq.h>
38 #include <mach/regs-gpio.h>
41 #include <plat/regs-irqtype.h>
62 * @reg_pending register holding pending irqs
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
75 struct s3c_irq_data *irqs; member
89 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask()
90 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/powernv/ |
| D | pci-cxl.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014-2016 IBM Corp.
7 #include <asm/pnv-pci.h>
14 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pnv_phb_to_cxl_mode()
15 struct pnv_phb *phb = hose->private_data; in pnv_phb_to_cxl_mode()
21 return -ENODEV; in pnv_phb_to_cxl_mode()
25 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); in pnv_phb_to_cxl_mode()
27 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); in pnv_phb_to_cxl_mode()
29 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); in pnv_phb_to_cxl_mode()
40 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pnv_cxl_alloc_hwirqs()
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/powernv/ |
| D | pci-cxl.c | 2 * Copyright 2014-2016 IBM Corp.
11 #include <asm/pnv-pci.h>
18 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pnv_phb_to_cxl_mode()
19 struct pnv_phb *phb = hose->private_data; in pnv_phb_to_cxl_mode()
25 return -ENODEV; in pnv_phb_to_cxl_mode()
29 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); in pnv_phb_to_cxl_mode()
31 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); in pnv_phb_to_cxl_mode()
33 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); in pnv_phb_to_cxl_mode()
44 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pnv_cxl_alloc_hwirqs()
45 struct pnv_phb *phb = hose->private_data; in pnv_cxl_alloc_hwirqs()
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-pmcs-msp71xx/ |
| D | msp_slp_int.h | 4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
29 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
31 * and are assigned the interrupt range 0-7. The second level is the SLM
32 * interrupt controller and is assigned the range 8-39. The third level
37 * the range 40-71.
41 * IRQs directly connected to CPU
54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
56 * interrupt routine. For now, just use hard-coded values.
67 /* Reserved 4-7 */
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| D | msp_cic_int.h | 4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
29 * The PMC-Sierra CIC interrupts are all centrally managed by the
30 * CIC sub-system.
34 * are assigned interrupts in the range 0-7, interrupts cascaded through
35 * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
38 * The PER interrupts are assigned interrupts in the range 40-71.
43 * IRQs directly forwarded to the CPU
56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
58 * interrupt routine. For now, just use hard-coded values.
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| /kernel/linux/linux-4.19/kernel/irq/ |
| D | matrix.c | 1 // SPDX-License-Identifier: GPL-2.0
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
80 struct cpumap *cm = this_cpu_ptr(m->maps); in irq_matrix_online()
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | matrix.c | 1 // SPDX-License-Identifier: GPL-2.0
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
80 struct cpumap *cm = this_cpu_ptr(m->maps); in irq_matrix_online()
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| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | intel_soc_pmic_mrfld.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Intel Corporation. All rights reserved.
50 /* Level 1 IRQs */
60 /* Level 2 IRQs: power button */
64 /* Level 2 IRQs: ADC */
71 /* Level 2 IRQs: charger */
|
| D | rohm-bd70528.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <linux/mfd/rohm-generic.h>
10 #include <linux/mfd/rohm-shared.h>
159 /* IRQs */
161 /* Shutdown register IRQs */
169 /* Power failure register IRQs */
178 /* VR FAULT register IRQs */
190 /* Charger 1 register IRQs */
199 /* Charger 2 register IRQs */
208 /* RTC register IRQs */
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| /kernel/linux/linux-4.19/arch/arm/mach-netx/include/mach/ |
| D | irqs.h | 2 * arch/arm/mach-netx/include/mach/irqs.h
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
49 /* int 27 is reserved */
50 /* int 28 is reserved */
53 /* int 31 is reserved */
57 /* for multiplexed irqs on gpio 0..14 */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
22 The property "ti,irqs-reserved" is used for denoting the connection
30 through 19) are connected to new sub-modules within the ICSSG instances.
32 This interrupt-controller node should be defined as a child node of the
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| /kernel/linux/linux-4.19/arch/mips/dec/ |
| D | int-handler.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Rewritten extensively for controller-driven IRQ support
50 * 3) Linux only thinks in terms of all IRQs on or all IRQs
51 * off, nothing in between like BSD spl() brain-damage.
53 * Furthermore, the IRQs on the DECstations look basically (barring
54 * software IRQs which we don't use at all) like...
59 * -------- ------
72 * -------- ------
77 * 4 Reserved
79 * 6 Reserved
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| /kernel/linux/linux-5.10/arch/mips/dec/ |
| D | int-handler.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Rewritten extensively for controller-driven IRQ support
50 * 3) Linux only thinks in terms of all IRQs on or all IRQs
51 * off, nothing in between like BSD spl() brain-damage.
53 * Furthermore, the IRQs on the DECstations look basically (barring
54 * software IRQs which we don't use at all) like...
59 * -------- ------
72 * -------- ------
77 * 4 Reserved
79 * 6 Reserved
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | irq-s3c24xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2003-2004 Simtec Electronics
28 #include <mach/irqs.h>
29 #include "regs-irq.h"
30 #include "regs-gpio.h"
33 #include "regs-irqtype.h"
54 * @reg_pending register holding pending irqs
58 * @parent parent controller for ext and sub irqs
59 * @irqs irq-data, always s3c_irq_data[32]
67 struct s3c_irq_data *irqs; member
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| /kernel/linux/linux-5.10/arch/mips/sgi-ip30/ |
| D | ip30-irq.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
17 #include "ip30-common.h"
35 return -ENOSPC; in heart_alloc_int()
49 pending = heart_read(&heart_regs->isr); in ip30_error_irq()
50 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
51 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
58 /* Prevent any of the error IRQs from firing again. */ in ip30_error_irq()
59 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
61 /* Ack all error IRQs. */ in ip30_error_irq()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,wcnss-pil.txt | 6 - compatible:
10 "qcom,riva-pil",
11 "qcom,pronto-v1-pil",
12 "qcom,pronto-v2-pil"
14 - reg:
16 Value type: <prop-encoded-array>
20 - reg-names:
25 - interrupts-extended:
27 Value type: <prop-encoded-array>
28 Definition: must list the watchdog and fatal IRQs and may specify the
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,wcnss-pil.txt | 6 - compatible:
10 "qcom,riva-pil",
11 "qcom,pronto-v1-pil",
12 "qcom,pronto-v2-pil"
14 - reg:
16 Value type: <prop-encoded-array>
20 - reg-names:
25 - interrupts-extended:
27 Value type: <prop-encoded-array>
28 Definition: must list the watchdog and fatal IRQs and may specify the
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| /kernel/linux/linux-5.10/include/linux/amba/ |
| D | bus.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
35 * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
37 * Remaining CID bits stay as 0xb105-00d
44 * the amba_id->data pointer.
96 /* This is used to generate pseudo-ID for AMBA device */
105 #define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
106 #define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
139 return clk_enable(dev->pclk); in amba_pclk_enable()
144 clk_disable(dev->pclk); in amba_pclk_disable()
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| /kernel/linux/linux-5.10/arch/arc/include/asm/ |
| D | irqflags-arcv2.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
12 #define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */
39 * Linux by default runs at 1, priority 0 reserved for NMI style interrupts
56 * Save IRQ state and disable IRQs
76 * Unconditionally Enable IRQs
89 * Unconditionally Disable IRQs
|