| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | cdns,cdns-pcie-ep.txt | 4 - compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
5 - reg: Should contain the controller register base address and AXI interface
7 - reg-names: Must be "reg" and "mem" respectively.
8 - cdns,max-outbound-regions: Set to maximum number of outbound regions
11 - max-functions: Maximum number of functions that can be configured (default 1).
12 - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
14 - phy-names: List of names to identify the PHY.
19 compatible = "cdns,cdns-pcie-ep";
22 reg-names = "reg", "mem";
23 cdns,max-outbound-regions = <16>;
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| D | rockchip-pcie-ep.txt | 4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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| D | cdns,cdns-pcie-host.txt | 4 host-generic-pci.txt.
7 - compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
8 - reg: Should contain the controller register base address, PCIe configuration
10 - reg-names: Must be "reg", "cfg" and "mem" respectively.
11 - #address-cells: Set to <3>
12 - #size-cells: Set to <2>
13 - device_type: Set to "pci"
14 - ranges: Ranges for the PCI memory and I/O regions
15 - #interrupt-cells: Set to <1>
16 - interrupt-map-mask and interrupt-map: Standard PCI properties to define the
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| D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: Should contain the configuration address space.
8 - reg-names: Must be "config" for the PCIe configuration space.
11 - num-lanes: number of lanes to use
13 - #address-cells: set to <3>
14 - #size-cells: set to <2>
15 - device_type: set to "pci"
16 - ranges: ranges for the PCI memory and I/O regions
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie.yaml#"
16 cdns,max-outbound-regions:
17 description: maximum number of outbound regions
24 - cdns,max-outbound-regions
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| D | rockchip-pcie-ep.txt | 4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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| D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
26 - const: intd_cfg
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| D | cdns-pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "/schemas/pci/pci-bus.yaml#"
14 - $ref: "cdns-pcie.yaml#"
17 cdns,max-outbound-regions:
18 description: maximum number of outbound regions
25 cdns,no-bar-match-nbits:
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| D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie-ep.yaml#"
14 - $ref: "pci-ep.yaml#"
18 const: cdns,cdns-pcie-ep
23 reg-names:
25 - const: reg
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| D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
14 #include "pcie-cadence.h"
21 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
23 * @max_regions: maximum number of regions supported by hardware
24 * @ob_region_map: bitmask of mapped outbound regions
25 * @ob_addr: base addresses in the AXI bus where the outbound regions start
27 * dedicated outbound regions is mapped.
32 * dedicated outbound region.
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| D | pcie-rockchip-ep.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
25 * @max_regions: maximum number of regions supported by hardware
26 * @ob_region_map: bitmask of mapped outbound regions
27 * @ob_addr: base addresses in the AXI bus where the outbound regions start
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| D | pcie-cadence-host.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
12 #include "pcie-cadence.h"
15 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
23 * @max_regions: maximum number of regions supported by the hardware
24 * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
46 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus()
47 unsigned int busn = bus->number; in cdns_pci_map_bus()
50 if (busn == rc->bus_range->start) { in cdns_pci_map_bus()
59 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
66 /* derive the enum index of the outbound/inbound mapping registers */
70 * Maximum number of outbound mapping window sizes that can be supported by any
95 * iProc PCIe outbound mapping controller specific parameters
97 * @window_sizes: list of supported outbound mapping window sizes in MB
98 * @nr_sizes: number of supported outbound mapping window sizes
165 * @imap_addr_offset: register offset between the upper and lower 32-bit
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-rockchip-ep.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
70 /* derive the enum index of the outbound/inbound mapping registers */
74 * Maximum number of outbound mapping window sizes that can be supported by any
99 * iProc PCIe outbound mapping controller specific parameters
101 * @window_sizes: list of supported outbound mapping window sizes in MB
102 * @nr_sizes: number of supported outbound mapping window sizes
169 * @imap_addr_offset: register offset between the upper and lower 32-bit
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| /kernel/linux/linux-5.10/drivers/scsi/pm8001/ |
| D | pm8001_defs.h | 2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
68 DATA_DIR_OUT = 0x02, /* OUTBOUND */
77 /* driver compile-time configuration */
78 #define PM8001_MAX_CCB 1024 /* max ccbs supported */
84 /* Inbound/Outbound queue size */
89 #define PM8001_MAX_PHYS 16 /* max. possible phys */
90 #define PM8001_MAX_PORTS 16 /* max. possible ports */
91 #define PM8001_MAX_DEVICES 2048 /* max supported device */
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header()
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
29 hdr->subclass_code | hdr->baseclass_code << 8); in cdns_pcie_ep_write_header()
31 hdr->cache_line_size); in cdns_pcie_ep_write_header()
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| /kernel/linux/linux-5.10/drivers/rapidio/devices/ |
| D | tsi721.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
47 * tsi721_lcread - read from local SREP config space
55 * success or %-EINVAL on failure.
60 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
63 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
65 *data = ioread32(priv->regs + offset); in tsi721_lcread()
71 * tsi721_lcwrite - write into local SREP config space
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| /kernel/linux/linux-4.19/drivers/rapidio/devices/ |
| D | tsi721.c | 2 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/dma-mapping.h>
45 static int pcie_mrrs = -1;
60 * tsi721_lcread - read from local SREP config space
68 * success or %-EINVAL on failure.
73 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
76 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
78 *data = ioread32(priv->regs + offset); in tsi721_lcread()
84 * tsi721_lcwrite - write into local SREP config space
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| /kernel/linux/linux-5.10/include/linux/ |
| D | rio.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 #define RIO_NO_HOPCOUNT -1
56 * 0 RapidIO outbound doorbells
57 * 1-15 RapidIO memory regions
63 * 2 RapidIO outbound mailboxes
89 * struct rio_switch - RIO switch info
92 * @port_ok: Status of each port (one bit per port) - OK=1 or UNINIT=0
93 * @ops: pointer to switch-specific operations
95 * @nextdev: Array of per-port pointers to the next attached device
107 * struct rio_switch_ops - Per-switch operations
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| /kernel/linux/linux-4.19/include/linux/ |
| D | rio.h | 28 #define RIO_NO_HOPCOUNT -1
60 * 0 RapidIO outbound doorbells
61 * 1-15 RapidIO memory regions
67 * 2 RapidIO outbound mailboxes
93 * struct rio_switch - RIO switch info
96 * @port_ok: Status of each port (one bit per port) - OK=1 or UNINIT=0
97 * @ops: pointer to switch-specific operations
99 * @nextdev: Array of per-port pointers to the next attached device
111 * struct rio_switch_ops - Per-switch operations
113 * @add_entry: Callback for switch-specific route add function
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
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| /kernel/linux/linux-4.19/drivers/scsi/esas2r/ |
| D | esas2r_init.c | 5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
21 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
40 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
50 mem_desc->esas2r_param = mem_desc->size + align; in esas2r_initmem_alloc()
51 mem_desc->virt_addr = NULL; in esas2r_initmem_alloc()
52 mem_desc->phys_addr = 0; in esas2r_initmem_alloc()
53 mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev, in esas2r_initmem_alloc()
54 (size_t)mem_desc-> in esas2r_initmem_alloc()
56 (dma_addr_t *)&mem_desc-> in esas2r_initmem_alloc()
60 if (mem_desc->esas2r_data == NULL) { in esas2r_initmem_alloc()
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| /kernel/linux/linux-5.10/drivers/scsi/esas2r/ |
| D | esas2r_init.c | 5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
21 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
40 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
50 mem_desc->esas2r_param = mem_desc->size + align; in esas2r_initmem_alloc()
51 mem_desc->virt_addr = NULL; in esas2r_initmem_alloc()
52 mem_desc->phys_addr = 0; in esas2r_initmem_alloc()
53 mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev, in esas2r_initmem_alloc()
54 (size_t)mem_desc-> in esas2r_initmem_alloc()
56 (dma_addr_t *)&mem_desc-> in esas2r_initmem_alloc()
60 if (mem_desc->esas2r_data == NULL) { in esas2r_initmem_alloc()
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