Searched +full:non +full:- +full:armv7 (Results 1 – 25 of 102) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | pmu.txt | 5 representation in the device tree should be done as under:-
9 - compatible : should be one of
10 "apm,potenza-pmu"
11 "arm,armv8-pmuv3"
12 "arm,cortex-a73-pmu"
13 "arm,cortex-a72-pmu"
14 "arm,cortex-a57-pmu"
15 "arm,cortex-a53-pmu"
16 "arm,cortex-a35-pmu"
17 "arm,cortex-a17-pmu"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.txt | 3 ARM cores may have a per-core architected timer, which provides per-cpu timers,
7 The per-core architected timer is attached to a GIC to deliver its
8 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
13 - compatible : Should at least contain one of
14 "arm,armv7-timer"
15 "arm,armv8-timer"
17 - interrupts : Interrupt list for secure, non-secure, virtual and
20 - clock-frequency : The frequency of the main counter, in Hz. Should be present
25 - always-on : a boolean property. If present, the timer is powered through an
26 always-on power domain, therefore it never loses context.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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| /kernel/linux/linux-4.19/Documentation/arm/Marvell/ |
| D | README | 12 ------------
19 …asheet : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
20 …'s User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.p…
21 … Manual : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
25 Core: Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible
26 Linux kernel mach directory: arch/arm/mach-orion5x
27 Linux kernel plat directory: arch/arm/plat-orion
30 ---------------
34 … Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
36 … Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | marvel.rst | 13 ------------
16 - 88F5082
17 - 88F5181
18 - 88F5181L
19 - 88F5182
21 … - Datasheet: http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
22 …- Programmer's User Guide: http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensour…
23 … - User Manual: http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
24 - 88F5281
26 …- Datasheet: http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sh…
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| D | kernel_mode_neon.rst | 6 -------------
10 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'
18 ------------
25 non-preemptible section for reasons outlined below.
29 -------------------------
50 ----------------------------
67 --------------------
69 like IEEE-754 compliant underflow handling etc. When the VFP unit needs such
80 ---------------------------------------
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
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| /kernel/liteos_a/arch/arm/arm/src/include/ |
| D | armv7_pmu_pri.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
53 #define ARMV7_PMNC_DP (1U << 5) /* Disable CCNT if non-invasive debug */
59 /* armv7 counters index */
65 #define ARMV7_IDX_COUNTER_LAST (ARMV7_IDX_CYCLE_COUNTER + ARMV7_MAX_COUNTERS - 1)
66 #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
68 /* armv7 event counter index mapping */
70 #define ARMV7_IDX2CNT(x) (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
76 ARMV7_PERF_HW_DCACHE_MISSES = 0x03, /* dcache-misses */
78 ARMV7_PERF_HW_ICACHE_MISSES = 0x01, /* icache-misses */
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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| /kernel/linux/linux-4.19/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /kernel/linux/linux-4.19/Documentation/trace/ |
| D | coresight-cpu-debug.txt | 8 ------------
10 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 debug module and it is mainly used for two modes: self-hosted debug and
15 explore debugging method which rely on self-hosted debug mode, this document
18 The debug module provides sample-based profiling extension, which can be used
20 every CPU has one dedicated debug module to be connected. Based on self-hosted
28 --------------
30 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
31 registers to decide if sample-based profiling is implemented or not. On some
35 - At the time this documentation was written, the debug driver mainly relies on
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | cacheflush.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King
12 #include <asm/glue-cache.h>
17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
35 * See Documentation/core-api/cachetlb.rst for more information.
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
52 * inner shareable and invalidate the I-cache.
65 * - start - user start address (inclusive, page aligned)
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| /kernel/linux/linux-4.19/arch/arm/include/asm/ |
| D | cacheflush.h | 4 * Copyright (C) 1999-2002 Russell King
15 #include <asm/glue-cache.h>
20 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
32 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
38 * See Documentation/core-api/cachetlb.rst for more information.
40 * effects are cache-type (VIVT/VIPT/PIPT) specific.
45 * Currently only needed for cache-v6.S and cache-v7.S, see
55 * inner shareable and invalidate the I-cache.
68 * - start - user start address (inclusive, page aligned)
69 * - end - user end address (exclusive, page aligned)
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| /kernel/linux/linux-4.19/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
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| /kernel/linux/linux-5.10/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
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| /kernel/linux/linux-5.10/tools/perf/util/ |
| D | cs-etm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
83 * table 6-12 Possible values for the TYPE field in an Exception instruction
84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
139 * When working with per-thread scenarios the process under trace can
188 return -1; in cs_etm__process_auxtrace_info()
194 return -1; in cs_etm__get_cpu()
202 return -1; in cs_etm__etmq_set_tid()
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| /kernel/linux/linux-4.19/Documentation/arm/Samsung/ |
| D | Bootloader-interface.txt | 12 In the document "boot loader" means any of following: U-boot, proprietary
13 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
17 1. Non-Secure mode
54 3. Other (regardless of secure/non-secure mode)
59 0x0908 Non-zero Secondary CPU boot up indicator
65 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
67 MCPM - Multi-Cluster Power Management
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
33 bool "ARMv7/v8 Long Descriptor Format"
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
52 bool "ARMv7/v8 Short Descriptor Format"
56 Enable support for the ARM Short-descriptor pagetable format.
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
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| /kernel/linux/linux-4.19/Documentation/arm/ |
| D | kernel_mode_neon.txt | 5 -------------
9 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'
17 ------------
24 non-preemptible section for reasons outlined below.
28 -------------------------
49 ----------------------------
66 --------------------
68 like IEEE-754 compliant underflow handling etc. When the VFP unit needs such
79 ---------------------------------------
83 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
[all …]
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| /kernel/linux/linux-5.10/Documentation/arm/samsung/ |
| D | bootloader-interface.rst | 14 In the document "boot loader" means any of following: U-boot, proprietary
15 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
19 1. Non-Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
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| /kernel/linux/linux-5.10/lib/raid6/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_RAID6_PQ) += raid6_pq.o
4 raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \
7 raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o recov_avx5…
8 raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o \
10 raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_ne…
11 raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o
16 altivec_flags := -maltivec $(call cc-option,-mabi=altivec)
19 # clang ppc port does not yet support -maltivec when -msoft-float is
22 CFLAGS_REMOVE_altivec1.o += -msoft-float
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| /kernel/linux/linux-4.19/drivers/iommu/ |
| D | Kconfig | 9 ---help---
24 bool "ARMv7/v8 Long Descriptor Format"
30 sizes at both stage-1 and stage-2, as well as address spaces
31 up to 48-bits in size.
37 Enable self-tests for LPAE page table allocator. This performs
38 a series of page-table consistency checks during boot.
43 bool "ARMv7/v8 Short Descriptor Format"
47 Enable support for the ARM Short-descriptor pagetable format.
48 This supports 32-bit virtual and physical addresses mapped using
49 2-level tables with 4KB pages/1MB sections, and contiguous entries
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | perf_event_v7.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
5 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
9 * by the ARMv7 Oprofile code.
11 * Cortex-A8 has up to 4 configurable performance counters and
13 * Cortex-A9 has up to 31 configurable performance counters and
33 * Common ARMv7 event types
55 * - all (taken) branch instructions,
56 * - instructions that explicitly write the PC,
57 * - exception generating instructions.
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