| /kernel/linux/linux-5.10/arch/arm/mach-sa1100/ |
| D | pci-nanoengine.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-sa1100/pci-nanoengine.c
7 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
14 #include <asm/mach-types.h>
22 if (bus->number != 0 || (devfn >> 3) != 0) in nanoengine_pci_map_bus()
26 ((bus->number << 16) | (devfn << 8) | (where & ~3)); in nanoengine_pci_map_bus()
45 .name = "PCI non-prefetchable",
49 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
50 /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
55 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
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| /kernel/linux/linux-4.19/arch/arm/mach-sa1100/ |
| D | pci-nanoengine.c | 2 * linux/arch/arm/mach-sa1100/pci-nanoengine.c
6 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <asm/mach-types.h>
35 if (bus->number != 0 || (devfn >> 3) != 0) in nanoengine_pci_map_bus()
39 ((bus->number << 16) | (devfn << 8) | (where & ~3)); in nanoengine_pci_map_bus()
58 .name = "PCI non-prefetchable",
62 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
63 /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
68 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
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| D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
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| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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| D | nvidia,tegra194-pcie.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
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| D | versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
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| D | layerscape-pci.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
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| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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| D | versatile.txt | 6 - compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
8 - reg: base addresses and lengths of the PCI controller. There must be 3
10 - Versatile-specific registers
11 - Self Config space
12 - Config space
13 - #address-cells: set to <3>
14 - #size-cells: set to <2>
15 - device_type: set to "pci"
16 - bus-range: set to <0 0xff>
17 - ranges: ranges for the PCI memory and I/O regions
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| D | layerscape-pci.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
16 "fsl,ls1021a-pcie", "snps,dw-pcie"
17 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
18 "fsl,ls2088a-pcie"
19 "fsl,ls1088a-pcie"
20 "fsl,ls1046a-pcie"
21 "fsl,ls1012a-pcie"
22 - reg: base addresses and lengths of the PCIe controller register blocks.
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
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| D | host-generic-pci.txt | 3 Firmware-initialised PCI host controllers and PCI emulations, such as the
4 virtio-pci implementations found in kvmtool and other para-virtualised
17 - compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
21 - device_type : Must be "pci".
23 - ranges : As described in IEEE Std 1275-1994, but must provide
24 at least a definition of non-prefetchable memory. One
25 or both of prefetchable Memory and IO Space may also
28 - bus-range : Optional property (also described in IEEE Std 1275-1994)
32 - #address-cells : Must be 3.
34 - #size-cells : Must be 2.
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| /kernel/linux/linux-5.10/drivers/pci/ |
| D | setup-bus.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * PCI-PCI bridges cleanup, sorted resource allocation.
14 * tighter packing. Prefetchable range support.
47 list_del(&dev_res->list); in free_list()
53 * add_to_list() - Add a new resource tracker to the list
68 return -ENOMEM; in add_to_list()
70 tmp->res = res; in add_to_list()
71 tmp->dev = dev; in add_to_list()
72 tmp->start = res->start; in add_to_list()
73 tmp->end = res->end; in add_to_list()
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| D | setup-res.c | 1 // SPDX-License-Identifier: GPL-2.0
32 struct resource *res = dev->resource + resno; in pci_std_update_resource()
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
35 if (dev->is_virtfn) in pci_std_update_resource()
42 if (!res->flags) in pci_std_update_resource()
45 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource()
49 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource()
53 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource()
56 pcibios_resource_to_bus(dev->bus, ®ion, res); in pci_std_update_resource()
59 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource()
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| /kernel/linux/linux-4.19/drivers/pci/ |
| D | setup-bus.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * PCI-PCI bridges cleanup, sorted resource allocation.
14 * tighter packing. Prefetchable range support.
46 list_del(&dev_res->list); in free_list()
52 * add_to_list() - add a new resource tracker to the list
68 return -ENOMEM; in add_to_list()
70 tmp->res = res; in add_to_list()
71 tmp->dev = dev; in add_to_list()
72 tmp->start = res->start; in add_to_list()
73 tmp->end = res->end; in add_to_list()
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| D | setup-res.c | 1 // SPDX-License-Identifier: GPL-2.0
32 struct resource *res = dev->resource + resno; in pci_std_update_resource()
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
35 if (dev->is_virtfn) in pci_std_update_resource()
42 if (!res->flags) in pci_std_update_resource()
45 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource()
49 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource()
53 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource()
56 pcibios_resource_to_bus(dev->bus, ®ion, res); in pci_std_update_resource()
59 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource()
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pci-v3-semi.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
136 /* PCI BASE bits (PCI -> Local Bus) */
143 /* PCI MAP bits (PCI -> Local bus) */
152 /* LB_BASE0,1 bits (Local bus -> PCI) */
174 /* LB_MAP0,1 bits (Local bus -> PCI) */
187 /* LB_BASE2 bits (Local bus -> PCI IO) */
194 /* LB_MAP2 bits (Local bus -> PCI IO) */
231 /* ARM Integrator-specific extended control registers */
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pci-v3-semi.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
136 /* PCI BASE bits (PCI -> Local Bus) */
143 /* PCI MAP bits (PCI -> Local bus) */
152 /* LB_BASE0,1 bits (Local bus -> PCI) */
174 /* LB_MAP0,1 bits (Local bus -> PCI) */
187 /* LB_BASE2 bits (Local bus -> PCI IO) */
194 /* LB_MAP2 bits (Local bus -> PCI IO) */
231 /* ARM Integrator-specific extended control registers */
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | versatile-pb.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | versatile-pb.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
26 #interrupt-cells = <2>;
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