Searched +full:system +full:- +full:clock +full:- +full:frequency (Results 1 – 25 of 1017) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/timers/ |
| D | timekeeping.txt | 1 Clock sources, Clock events, sched_clock() and delay timers
2 -----------------------------------------------------------
9 If you grep through the kernel source you will find a number of architecture-
10 specific implementations of clock sources, clockevents and several likewise
11 architecture-specific overrides of the sched_clock() function and some
14 To provide timekeeping for your platform, the clock source provides
15 the basic timeline, whereas clock events shoot interrupts on certain points
16 on this timeline, providing facilities such as high-resolution timers.
21 Clock sources
22 -------------
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| /kernel/linux/linux-5.10/Documentation/timers/ |
| D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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| /kernel/linux/linux-4.19/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | mpc5121.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | brcm,bcm2835-system-timer.txt | 1 BCM2835 System Timer
3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
|
| D | arm,arch_timer.txt | 3 ARM cores may have a per-core architected timer, which provides per-cpu timers,
7 The per-core architected timer is attached to a GIC to deliver its
8 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
13 - compatible : Should at least contain one of
14 "arm,armv7-timer"
15 "arm,armv8-timer"
17 - interrupts : Interrupt list for secure, non-secure, virtual and
20 - clock-frequency : The frequency of the main counter, in Hz. Should be present
25 - always-on : a boolean property. If present, the timer is powered through an
26 always-on power domain, therefore it never loses context.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | brcm,bcm2835-system-timer.txt | 1 BCM2835 System Timer
3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ptp/ |
| D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 - reg Offset and length of the register set for the device
8 - interrupts There should be at least two interrupts. Some devices
11 Clock Properties:
13 - fsl,cksel Timer reference clock source.
14 - fsl,tclk-period Timer reference clock period in nanoseconds.
15 - fsl,tmr-prsc Prescaler, divides the output clock.
16 - fsl,tmr-add Frequency compensation value.
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| /kernel/linux/linux-5.10/include/linux/ |
| D | ptp_clock_kernel.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PTP 1588 clock support
31 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
39 * struct ptp_clock_info - describes a PTP hardware clock
41 * @owner: The clock driver should set to THIS_MODULE.
42 * @name: A short "friendly name" to identify the clock and to
45 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
50 * @pps: Indicates whether the clock supports a PPS callback.
55 * clock operations
57 * @adjfine: Adjusts the frequency of the hardware clock.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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| D | at91-clock.txt | 1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc" or
10 "atmel,sama5d4-sckc":
11 at91 SCKC (Slow Clock Controller)
12 This node contains the slow clock definitions.
14 "atmel,at91sam9x5-clk-slow-osc":
17 "atmel,at91sam9x5-clk-slow-rc-osc":
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| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ptp/ |
| D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/ |
| D | ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfreq - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency change in parts per billion
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
29 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfreq()
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| /kernel/linux/linux-4.19/Documentation/ABI/testing/ |
| D | sysfs-devices-system-cpu | 1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
10 /sys/devices/system/cpu/cpu#/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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| /kernel/linux/linux-4.19/drivers/net/ethernet/intel/e1000e/ |
| D | ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfreq - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency change in parts per billion
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
29 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfreq()
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| /kernel/linux/linux-4.19/drivers/firmware/ |
| D | ti_sci.h | 1 // SPDX-License-Identifier: BSD-3-Clause
3 * Texas Instruments System Control Interface (TISCI) Protocol
6 * The system works in a message response protocol
9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
28 /* Clock requests */
39 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
60 * struct ti_sci_msg_resp_version - Response for a message
82 * struct ti_sci_msg_req_reboot - Reboot the SoC
93 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
100 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
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| /kernel/liteos_m/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/ |
| D | system_demosoc.c | 2 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
11 * www.apache.org/licenses/LICENSE-2.0
30 /*----------------------------------------------------------------------------
32 *----------------------------------------------------------------------------*/
38 * \defgroup NMSIS_Core_SystemConfig System Device Configuration
39 * \brief Functions for system and clock setup available in system_<device>.c.
44 * - A device-specific system configuration function, \ref SystemInit.
45 * - A global variable that contains the system frequency, \ref SystemCoreClock.
46 * - A global eclic configuration initialization, \ref ECLIC_Init.
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| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/ |
| D | system_gd32vf103.c | 9 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
12 * SPDX-License-Identifier: Apache-2.0
18 * www.apache.org/licenses/LICENSE-2.0
31 /*----------------------------------------------------------------------------
33 *----------------------------------------------------------------------------*/
39 * \defgroup NMSIS_Core_SystemAndClock System and Clock Configuration
40 * \brief Functions for system and clock setup available in system_<device>.c.
45 * - A device-specific system configuration function, \ref SystemInit().
46 * - A global variable that contains the system frequency, \ref SystemCoreClock.
50 * a more flexible configuration of the microcontroller system.
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| /kernel/linux/linux-4.19/include/linux/ |
| D | ptp_clock_kernel.h | 2 * PTP 1588 clock support
43 * struct ptp_clock_info - decribes a PTP hardware clock
45 * @owner: The clock driver should set to THIS_MODULE.
46 * @name: A short "friendly name" to identify the clock and to
49 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
54 * @pps: Indicates whether the clock supports a PPS callback.
59 * clock operations
61 * @adjfine: Adjusts the frequency of the hardware clock.
62 * parameter scaled_ppm: Desired frequency offset from
63 * nominal frequency in parts per million, but with a
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 clock from a group of clients. Typically, a system has a single Arbitration
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-emc.txt | 4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
14 Child device nodes describe the memory settings for different configurations and clock rates.
18 memory-controller@7000f400 {
19 #address-cells = < 1 >;
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