Searched +full:tx +full:- +full:fifo +full:- +full:depth (Results 1 – 25 of 286) sorted by relevance
12345678910>>...12
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
15 - "can_clk", "pclk" (For CANPS),
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - reg : Physical base address and size of the controller
11 - interrupts : Property with a value describing the interrupt
13 - clock-names : List of input clock names
14 - "can_clk", "pclk" (For CANPS),
15 - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD).
[all …]
|
| /kernel/linux/linux-4.19/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
12 "tx_csr": xDMA Tx dispatcher control and status space region
13 "tx_desc": MSGDMA Tx dispatcher descriptor space region
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
[all …]
|
| D | ethernet.txt | 5 Documentation/devicetree/bindings/phy/phy-bindings.txt.
7 - local-mac-address: array of 6 bytes, specifies the MAC address that was
9 - mac-address: array of 6 bytes, specifies the MAC address that was last used by
11 the device by the boot program is different from the "local-mac-address"
13 - nvmem-cells: phandle, reference to an nvmem node for the MAC address;
14 - nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
15 - max-speed: number, specifies maximum speed in Mbit/s supported by the device;
16 - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
19 - phy-mode: string, operation mode of the PHY interface. This is now a de-facto
27 * "rev-mii"
[all …]
|
| D | ti,dp83867.txt | 1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
11 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
15 - ti,min-output-impedance - MAC Interface Impedance control to set
18 - ti,max-output-impedance - MAC Interface Impedance control to set
21 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
28 - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
31 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
[all …]
|
| D | stmmac.txt | 4 - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" or
5 "snps,dwxgmac-<ip_version>", "snps,dwxgmac".
6 For backwards compatibility: "st,spear600-gmac" is also supported.
7 - reg: Address and length of the register set for the device
8 - interrupts: Should contain the STMMAC interrupts
9 - interrupt-names: Should contain a list of interrupt names corresponding to
12 - "macirq" (combined signal for various interrupt events)
13 - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)
14 - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state)
15 - phy-mode: See ethernet.txt file in the same directory.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
12 "tx_csr": xDMA Tx dispatcher control and status space region
13 "tx_desc": MSGDMA Tx dispatcher descriptor space region
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
[all …]
|
| D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
40 ti,max-output-impedance:
45 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
[all …]
|
| D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
|
| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
[all …]
|
| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
19 $ref: /schemas/types.yaml#definitions/uint8-array
21 - minItems: 6
24 mac-address:
29 local-mac-address property.
[all …]
|
| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
28 - enum:
[all …]
|
| /kernel/linux/linux-4.19/include/linux/ |
| D | qcom-geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
29 * struct geni_se - GENI Serial Engine
178 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
242 * geni_se_read_proto() - Read the protocol configured for a serial engine
251 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
257 * geni_se_setup_m_cmd() - Setup the primary sequencer
270 writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
274 * geni_se_setup_s_cmd() - Setup the secondary sequencer
286 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc.txt | 11 - snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12 * #address-cells: should be 1.
13 * #size-cells: should be 0.
16 child-nodes with each child-node representing a supported slot. There should
23 property is 0 to (num-slots -1), where num-slots is the value
24 specified by the num-slots property.
26 * bus-width: as documented in mmc core bindings.
28 * wp-gpios: specifies the write protect gpio line. The format of the
30 for write-protect, this property is optional.
32 * disable-wp: If the wp-gpios property isn't present then (by default)
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | qcom-geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
42 * struct geni_se - GENI Serial Engine
197 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
274 * geni_se_read_proto() - Read the protocol configured for a serial engine
283 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
289 * geni_se_setup_m_cmd() - Setup the primary sequencer
302 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
306 * geni_se_setup_s_cmd() - Setup the secondary sequencer
318 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 17 /dts-v1/;
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/ |
| D | fsl,esai.txt | 3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, must contain "fsl,imx35-esai" or
11 "fsl,vf610-esai"
13 - reg : Offset and length of the register set for the device.
15 - interrupts : Contains the spdif interrupt.
17 - dmas : Generic dma devicetree binding as described in
20 - dma-names : Two dmas have to be defined, "tx" and "rx".
22 - clocks : Contains an entry for each entry in clock-names.
24 - clock-names : Includes the following entries:
36 - fsl,fifo-depth : The number of elements in the transmit and receive
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | fsl,esai.txt | 3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
15 "fsl,imx8qm-esai",
17 - reg : Offset and length of the register set for the device.
19 - interrupts : Contains the spdif interrupt.
21 - dmas : Generic dma devicetree binding as described in
24 - dma-names : Two dmas have to be defined, "tx" and "rx".
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/ethernet/sgi/ |
| D | meth.h | 3 * snull.h -- definitions for the network module
20 #define TX_RING_ENTRIES 64 /* 64-512?*/
27 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
35 /* tx status vector is written over tx command header upon
48 * It consists of header, 0-3 concatination
56 u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
59 u64 data_len:16; /*Length of valid data in bytes-1*/
64 u64 len:16; /*length of buffer data - 1*/
107 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
109 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/sgi/ |
| D | meth.h | 4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
19 /* tx status vector is written over tx command header upon
32 * It consists of header, 0-3 concatination
40 u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
[all …]
|
| /kernel/linux/linux-4.19/arch/arc/boot/dts/ |
| D | hsdk.dts | 12 /dts-v1/;
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 #address-cells = <1>;
34 #size-cells = <0>;
65 input_clk: input-clk {
66 #clock-cells = <0>;
[all …]
|
| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/Usb/ |
| D | drv_usb_regs.h | 5 \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
43 #define USBFS_MAX_TX_FIFOS 15 /*!< FIFO number */
48 #define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */
53 #define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */
55 #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
56 #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
73 USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */
88 …__IO uint32_t GRFLEN; /*!< USB global receive FIFO length register …
89 …LEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length re…
90 …__IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status regis…
[all …]
|
12345678910>>...12