| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-ns-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
56 struct phy *phy; member
58 int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value);
63 .compatible = "brcm,ns-ax-usb3-phy",
67 .compatible = "brcm,ns-bx-usb3-phy",
74 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, in bcm_ns_usb3_mdio_phy_write() argument
77 return usb3->phy_write(usb3, reg, value); in bcm_ns_usb3_mdio_phy_write()
80 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
[all …]
|
| /kernel/linux/linux-4.19/drivers/phy/broadcom/ |
| D | phy-bcm-ns-usb3.c | 2 * Broadcom Northstar USB 3.0 PHY Driver
24 #include <linux/phy/phy.h>
58 struct phy *phy; member
60 int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value);
65 .compatible = "brcm,ns-ax-usb3-phy",
69 .compatible = "brcm,ns-bx-usb3-phy",
76 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, in bcm_ns_usb3_mdio_phy_write() argument
79 return usb3->phy_write(usb3, reg, value); in bcm_ns_usb3_mdio_phy_write()
82 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
86 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
|
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
|
| D | socionext,uniphier-usb3ss-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
|
| D | qcom,qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
[all …]
|
| D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
|
| D | bcm-ns-usb3-phy.txt | 1 Driver for Broadcom Northstar USB 3.0 PHY
5 - compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
6 - reg: address of MDIO bus device
7 - usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
9 - #phy-cells: must be 0
11 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
21 #size-cells = <1>;
22 #address-cells = <0>;
24 usb3-phy@10 {
25 compatible = "brcm,ns-ax-usb3-phy";
[all …]
|
| D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
[all …]
|
| D | amlogic,meson-g12a-usb3-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson-g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
[all …]
|
| D | allwinner,sun50i-h6-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Allwinner H6 USB3 PHY
11 - Ondrej Jirman <megous@megous.com>
16 - allwinner,sun50i-h6-usb3-phy
27 "#phy-cells":
31 - compatible
32 - reg
[all …]
|
| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | rcar-gen3-phy-usb3.txt | 1 * Renesas R-Car generation 3 USB 3.0 PHY
3 This file provides information on what the device node for the R-Car generation
4 3 USB 3.0 PHY contains.
10 - compatible: "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
12 "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
14 "renesas,r8a77965-usb3-phy" if the device is a part of an
16 "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
20 SoC-specific version corresponding to the platform first
23 - reg: offset and length of the USB 3.0 PHY register block.
24 - clocks: A list of phandles and clock-specifier pairs.
[all …]
|
| D | qcom-qmp-phy.txt | 1 Qualcomm QMP PHY controller
4 QMP phy controller supports physical layer functionality for a number of
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
15 - reg:
16 - For "qcom,sdm845-qmp-usb3-phy":
[all …]
|
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
|
| D | bcm-ns-usb3-phy.txt | 1 Driver for Broadcom Northstar USB 3.0 PHY
5 - compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
6 - reg: address of MDIO bus device
7 - usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
9 - #phy-cells: must be 0
11 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
21 #size-cells = <1>;
22 #address-cells = <0>;
24 usb3-phy@10 {
25 compatible = "brcm,ns-ax-usb3-phy";
[all …]
|
| D | meson-gxl-usb3-phy.txt | 1 * Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
4 - compatible: Should be "amlogic,meson-gxl-usb3-phy"
5 - #phys-cells: must be 0 (see phy-bindings.txt in this directory)
6 - reg: The base address and length of the registers
7 - interrupts: the interrupt specifier for the OTG detection
8 - clocks: phandles to the clocks for
9 - the USB3 PHY
10 - and peripheral mode/OTG detection
11 - clock-names: must contain "phy" and "peripheral"
12 - resets: phandle to the reset lines for:
[all …]
|
| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/phy/phy.h>
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
149 /* USB 2.0 UTMI PHY support */
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
[all …]
|
| D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
15 - reg-names: Must contain the following entries:
16 - "hcd"
17 - "fpci"
[all …]
|
| D | qcom,dwc3.txt | 4 - compatible: Compatible list, contains
6 "qcom,msm8996-dwc3" for msm8996 SOC.
7 "qcom,sdm845-dwc3" for sdm845 SOC.
8 - reg: Offset and length of register set for QSCRATCH wrapper
9 - power-domains: specifies a phandle to PM domain provider node
10 - clocks: A list of phandle + clock-specifier pairs for the
11 clocks listed in clock-names
12 - clock-names: Should contain the following:
17 "sleep" Sleep clock, used for wakeup when USB3 core goes
22 Not present on "qcom,msm8996-dwc3" compatible.
[all …]
|
| D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: should contain "ref", "bus_early", "suspend"
11 - clocks: list of phandle and clock specifier pairs corresponding to
12 entries in the clock-names property.
15 clocks are optional if the parent node (i.e. glue-layer) is compatible to
17 "amlogic,meson-axg-dwc3"
18 "amlogic,meson-gxl-dwc3"
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/socionext/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
[all …]
|