Searched refs:DDRC1_CTRL_SREF_OFST (Results 1 – 8 of 8) sorted by relevance
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/ |
| D | lowlevel_init_v300.c | 40 #define DDRC1_CTRL_SREF_OFST (0x9000 + 0x0) macro
203 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
235 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1 << 1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/ |
| D | lowlevel_init_v300.c | 37 #define DDRC1_CTRL_SREF_OFST 0x9000 + 0x0 macro
178 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
212 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1<<1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/ |
| D | lowlevel_init_v300.c | 37 #define DDRC1_CTRL_SREF_OFST 0x9000 + 0x0 macro
178 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
212 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1<<1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/ |
| D | lowlevel_init_v300.c | 37 #define DDRC1_CTRL_SREF_OFST 0x9000 + 0x0 macro
177 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
256 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1<<1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/ |
| D | lowlevel_init_v300.c | 39 #define DDRC1_CTRL_SREF_OFST (0x9000 + 0x0) macro
200 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
230 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1 << 1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/ |
| D | lowlevel_init_v300.c | 37 #define DDRC1_CTRL_SREF_OFST 0x9000 + 0x0 macro
177 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
256 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1<<1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/ |
| D | lowlevel_init_v300.c | 40 #define DDRC1_CTRL_SREF_OFST (0x9000 + 0x0) macro
198 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
238 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1 << 1)); in ddr_scramb()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/ |
| D | lowlevel_init_v300.c | 40 #define DDRC1_CTRL_SREF_OFST (0x9000 + 0x0) macro
198 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, 0x1); in ddr_scramb()
238 reg_set(REG_BASE_DDRC + DDRC1_CTRL_SREF_OFST, (0x1 << 1)); in ddr_scramb()
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