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Searched refs:DDRC2_CFG_DDRMODE_OFST (Results 1 – 8 of 8) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/
Dlowlevel_init_v300.c42 #define DDRC2_CFG_DDRMODE_OFST 0xa000 + 0X50 macro
171 ddrc_isvalid[2] = (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/
Dlowlevel_init_v300.c42 #define DDRC2_CFG_DDRMODE_OFST 0xa000 + 0X50 macro
171 ddrc_isvalid[2] = (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/
Dlowlevel_init_v300.c42 #define DDRC2_CFG_DDRMODE_OFST 0xa000 + 0X50 macro
170 ddrc_isvalid[2] = (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST)& 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/
Dlowlevel_init_v300.c42 #define DDRC2_CFG_DDRMODE_OFST 0xa000 + 0X50 macro
170 ddrc_isvalid[2] = (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST)& 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/
Dlowlevel_init_v300.c45 #define DDRC2_CFG_DDRMODE_OFST (0xa000 + 0X50) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/
Dlowlevel_init_v300.c45 #define DDRC2_CFG_DDRMODE_OFST (0xa000 + 0X50) macro
189 (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/
Dlowlevel_init_v300.c45 #define DDRC2_CFG_DDRMODE_OFST (0xa000 + 0X50) macro
189 (reg_get(REG_BASE_DDRC + DDRC2_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/
Dlowlevel_init_v300.c44 #define DDRC2_CFG_DDRMODE_OFST (0xa000 + 0X50) macro