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Searched refs:DDRC_CFG_DDRMODE_OFST (Results 1 – 15 of 15) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/
Dlowlevel_init_v300.c37 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0X50) macro
194 (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/
Dlowlevel_init_v300.c34 #define DDRC_CFG_DDRMODE_OFST 0x8000 + 0X50 macro
169 ddrc_isvalid[0] = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/
Dlowlevel_init_v300.c74 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
158 ddrc_isvalid = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/
Dlowlevel_init_v300.c74 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
158 ddrc_isvalid = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/
Dlowlevel_init_v300.c73 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
151 ddrc_isvalid = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/
Dlowlevel_init_v300.c34 #define DDRC_CFG_DDRMODE_OFST 0x8000 + 0X50 macro
169 ddrc_isvalid[0] = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/
Dlowlevel_init_v300.c34 #define DDRC_CFG_DDRMODE_OFST 0x8000 + 0X50 macro
168 ddrc_isvalid[0] = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/
Dlowlevel_init_v300.c36 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0X50) macro
191 (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/
Dlowlevel_init_v300.c34 #define DDRC_CFG_DDRMODE_OFST 0x8000 + 0X50 macro
168 ddrc_isvalid[0] = (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf)?1:0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/
Dlowlevel_init_v300.c37 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0X50) macro
185 (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/
Dlowlevel_init_v300.c37 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0X50) macro
185 (reg_get(REG_BASE_DDRC + DDRC_CFG_DDRMODE_OFST) & 0xf) ? 1 : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/
Dlowlevel_init_v300.c72 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/
Dlowlevel_init_v300.c72 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/
Dlowlevel_init_v300.c72 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/
Dlowlevel_init_v300.c73 #define DDRC_CFG_DDRMODE_OFST (0x8000 + 0x50) macro