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Searched refs:DDRC_CURR_FUNC_OFST (Results 1 – 15 of 15) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/
Dlowlevel_init_v300.c38 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
208 (reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1) : 1; in ddr_scramb()
240 (reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/
Dlowlevel_init_v300.c35 #define DDRC_CURR_FUNC_OFST 0x8000 + 0x294 macro
186 …reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_M… in ddr_scramb()
220 …reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_M… in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/
Dlowlevel_init_v300.c75 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
167 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 1; in ddr_scramb()
193 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/
Dlowlevel_init_v300.c75 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
168 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 1; in ddr_scramb()
195 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/
Dlowlevel_init_v300.c74 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
159 reg_val = ddrc_isvalid ? (reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & in ddr_scramb()
187 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/
Dlowlevel_init_v300.c35 #define DDRC_CURR_FUNC_OFST 0x8000 + 0x294 macro
186 …reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_M… in ddr_scramb()
220 …reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_M… in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/
Dlowlevel_init_v300.c35 #define DDRC_CURR_FUNC_OFST 0x8000 + 0x294 macro
185 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1):1; in ddr_scramb()
264 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1):0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/
Dlowlevel_init_v300.c37 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
205 (reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1) : 1; in ddr_scramb()
235 (reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/
Dlowlevel_init_v300.c35 #define DDRC_CURR_FUNC_OFST 0x8000 + 0x294 macro
185 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1):1; in ddr_scramb()
264 reg_val[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & 0x1):0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/
Dlowlevel_init_v300.c38 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
209 DDRC_CURR_FUNC_OFST) & 0x1) : 1; in ddr_scramb()
249 DDRC_CURR_FUNC_OFST) & 0x1) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/
Dlowlevel_init_v300.c38 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
209 DDRC_CURR_FUNC_OFST) & 0x1) : 1; in ddr_scramb()
249 DDRC_CURR_FUNC_OFST) & 0x1) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/
Dlowlevel_init_v300.c73 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/
Dlowlevel_init_v300.c73 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/
Dlowlevel_init_v300.c73 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/
Dlowlevel_init_v300.c74 #define DDRC_CURR_FUNC_OFST (0x8000 + 0x294) macro