Home
last modified time | relevance | path

Searched refs:DDRC_SELF_REFURBISH_MASK (Results 1 – 15 of 15) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/
Dlowlevel_init_v300.c49 #define DDRC_SELF_REFURBISH_MASK (0x1) macro
186 …l[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
187 …[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
188 …[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
189 …[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
220 …l[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
221 …[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
222 …[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
223 …[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/
Dlowlevel_init_v300.c49 #define DDRC_SELF_REFURBISH_MASK (0x1) macro
186 …l[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
187 …[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
188 …[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
189 …[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):1; in ddr_scramb()
220 …l[0] = ddrc_isvalid[0]?(reg_get(REG_BASE_DDRC + DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
221 …[1] = ddrc_isvalid[1]?(reg_get(REG_BASE_DDRC + DDRC1_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
222 …[2] = ddrc_isvalid[2]?(reg_get(REG_BASE_DDRC + DDRC2_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
223 …[3] = ddrc_isvalid[3]?(reg_get(REG_BASE_DDRC + DDRC3_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK):0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/
Dlowlevel_init_v300.c78 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
167 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 1; in ddr_scramb()
193 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/
Dlowlevel_init_v300.c78 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
168 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 1; in ddr_scramb()
195 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/
Dlowlevel_init_v300.c77 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
160 DDRC_SELF_REFURBISH_MASK) : 1; in ddr_scramb()
187 DDRC_CURR_FUNC_OFST) & DDRC_SELF_REFURBISH_MASK) : 0; in ddr_scramb()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/
Dlowlevel_init_v300.c52 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/
Dlowlevel_init_v300.c76 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/
Dlowlevel_init_v300.c76 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/
Dlowlevel_init_v300.c76 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/
Dlowlevel_init_v300.c77 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/
Dlowlevel_init_v300.c49 #define DDRC_SELF_REFURBISH_MASK (0x1) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/
Dlowlevel_init_v300.c51 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/
Dlowlevel_init_v300.c49 #define DDRC_SELF_REFURBISH_MASK (0x1) macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/
Dlowlevel_init_v300.c52 #define DDRC_SELF_REFURBISH_MASK 0x1 macro
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/
Dlowlevel_init_v300.c52 #define DDRC_SELF_REFURBISH_MASK 0x1 macro