| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3520dv500/ |
| D | lowlevel_init_v300.c | 28 #define DDR_CA0_OFST 0x24 macro
93 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
98 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/ |
| D | lowlevel_init_v300.c | 68 #define DDR_CA0_OFST 0x28 macro
138 reg_set(REG_BASE_MISC + DDR_CA0_OFST, random1); in ddr_scramb_start()
143 reg_set(REG_BASE_MISC + DDR_CA0_OFST, 0); in ddr_scramb_start()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/ |
| D | lowlevel_init_v300.c | 68 #define DDR_CA0_OFST 0x28 macro
138 reg_set(REG_BASE_MISC + DDR_CA0_OFST, random1); in ddr_scramb_start()
143 reg_set(REG_BASE_MISC + DDR_CA0_OFST, 0); in ddr_scramb_start()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/ |
| D | lowlevel_init_v300.c | 67 #define DDR_CA0_OFST 0x28 macro
131 reg_set(REG_BASE_MISC + DDR_CA0_OFST, random1); in ddr_scramb_start()
136 reg_set(REG_BASE_MISC + DDR_CA0_OFST, 0); in ddr_scramb_start()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3521dv200/ |
| D | lowlevel_init_v300.c | 28 #define DDR_CA0_OFST 0x24 macro
93 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
98 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3535av100/ |
| D | lowlevel_init_v300.c | 28 #define DDR_CA0_OFST 0x24 macro
92 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
97 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3531dv200/ |
| D | lowlevel_init_v300.c | 28 #define DDR_CA0_OFST 0x24 macro
92 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
97 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/ |
| D | lowlevel_init_v300.c | 31 #define DDR_CA0_OFST 0x88 macro
111 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
116 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/ |
| D | lowlevel_init_v300.c | 31 #define DDR_CA0_OFST 0x88 macro
111 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), random1); in ddr_scramb_start()
116 reg_set((unsigned int *)(REG_BASE_MISC + DDR_CA0_OFST), 0); in ddr_scramb_start()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/ |
| D | lowlevel_init_v300.c | 31 #define DDR_CA0_OFST 0x88 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/ |
| D | lowlevel_init_v300.c | 66 #define DDR_CA0_OFST 0x28 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/ |
| D | lowlevel_init_v300.c | 66 #define DDR_CA0_OFST 0x28 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/ |
| D | lowlevel_init_v300.c | 66 #define DDR_CA0_OFST 0x28 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/ |
| D | lowlevel_init_v300.c | 67 #define DDR_CA0_OFST 0x28 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/ |
| D | lowlevel_init_v300.c | 31 #define DDR_CA0_OFST 0x88 macro
|