| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/ |
| D | ddr_training_ctl.c | 52 if (DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL in ddr_sw_training_func()
61 ddr_write(0x0, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); in ddr_sw_training_func()
231 unsigned int tmp_reg = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_VERSION_FLAG); in ddr_sw_training_func()
233 ddr_write(tmp_reg, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_VERSION_FLAG); in ddr_sw_training_func()
237 if (DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG) in ddr_sw_training_func()
239 && DDR_BYPASS_ALL_MASK == ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC) in ddr_sw_training_func()
251 ddr_write(0x0, DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_STAT); in ddr_sw_training_func()
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| D | ddr_cmd_ctl.c | 487 cfg = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_cmd_is_disable()
495 cfg = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC); in ddr_cmd_is_disable()
524 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG), in ddr_cmd_get_entry()
525 ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG)); in ddr_cmd_get_entry()
529 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC), in ddr_cmd_get_entry()
530 ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC)); in ddr_cmd_get_entry()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/ |
| D | ddr_training_custom.c | 44 reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
45 ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
71 ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 65 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/ |
| D | ddr_training_custom.c | 44 reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
45 ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
71 ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 65 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/ |
| D | ddr_training_custom.c | 44 reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
45 ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
71 ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 65 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/ |
| D | ddr_training_custom.c | 44 reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
45 ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
71 ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 65 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/ |
| D | ddr_training_custom.c | 80 relate_reg->custom.ddr_ctrl = ddr_read(DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
82 (0x1 << DDRT1_MST_SEL_BIT), DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddr_ctrl, DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/ |
| D | ddr_training_custom.c | 79 relate_reg->custom.ddr_ctrl = ddr_read(DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
80 …ddr_write(relate_reg->custom.ddr_ctrl | (0x1 << DDRT0_MST_SEL_BIT), DDR_REG_BASE_SYSCTRL + DDRT_CT… in ddr_boot_cmd_save()
110 ddr_write(relate_reg->custom.ddr_ctrl, DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/ |
| D | ddr_training_custom.c | 79 relate_reg->custom.ddr_ctrl = ddr_read(DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
80 …ddr_write(relate_reg->custom.ddr_ctrl | (0x1 << DDRT0_MST_SEL_BIT), DDR_REG_BASE_SYSCTRL + DDRT_CT… in ddr_boot_cmd_save()
110 ddr_write(relate_reg->custom.ddr_ctrl, DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/ |
| D | ddr_training_custom.c | 80 relate_reg->custom.ddr_ctrl = ddr_read(DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
82 (0x1 << DDRT1_MST_SEL_BIT), DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddr_ctrl, DDR_REG_BASE_SYSCTRL + DDRT_CTRL); in ddr_boot_cmd_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/cmd_bin/ |
| D | ddr_training_cmd.c | 436 DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cmd_func()
441 DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cmd_func()
470 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG), in ddr_training_cmd_entry()
471 ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG)); in ddr_training_cmd_entry()
475 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC), in ddr_training_cmd_entry()
476 ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC)); in ddr_training_cmd_entry()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/ |
| D | lowlevel_init_v300.c | 294 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
314 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
316 DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
348 writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/ |
| D | lowlevel_init_v300.c | 290 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
310 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
312 DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
344 writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/ |
| D | lowlevel_init_v300.c | 293 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
313 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
315 DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
347 writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/ |
| D | lowlevel_init_v300.c | 295 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
315 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
317 DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
349 writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3519av100/ |
| D | ddr_training_custom.h | 65 #define DDR_REG_BASE_SYSCTRL 0x04520000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3556av100/ |
| D | ddr_training_custom.h | 66 #define DDR_REG_BASE_SYSCTRL 0x04520000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/ |
| D | ddr_training_custom.h | 64 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/ |
| D | ddr_training_custom.h | 64 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3559av100/ |
| D | ddr_training_custom.h | 61 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/ |
| D | ddr_training_custom.h | 64 #define DDR_REG_BASE_SYSCTRL 0x12020000 macro
|