| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/ |
| D | imx_bootaux.c | 31 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, in arch_auxiliary_core_up()
45 val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); in arch_auxiliary_core_check_up()
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| D | init.c | 91 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in init_src()
107 struct src *psrc = (struct src *)SRC_BASE_ADDR; in boot_mode_apply()
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| D | cpu.c | 32 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause()
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx7/ |
| D | psci-mx7.c | 106 (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
175 val = readl(SRC_BASE_ADDR + SRC_A7RCR1); in imx_enable_cpu_ca7()
177 writel(val, SRC_BASE_ADDR + SRC_A7RCR1); in imx_enable_cpu_ca7()
683 writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D); in psci_system_suspend()
684 writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D); in psci_system_suspend()
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| D | ddr.c | 31 struct src *const src_regs = (struct src *)SRC_BASE_ADDR; in mx7_dram_cfg()
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| /third_party/uboot/u-boot-2020.01/board/grinn/liteboard/ |
| D | board.c | 79 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); in mmc_get_env_devno()
235 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_boot_order()
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx7ulp/ |
| D | soc.c | 265 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); in get_reset_cause()
266 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20); in get_reset_cause()
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| /third_party/uboot/u-boot-2020.01/include/configs/ |
| D | mx7ulp_evk.h | 17 #define SRC_BASE_ADDR CMC1_RBASE macro
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/ |
| D | mp.c | 17 static struct src *src = (struct src *)SRC_BASE_ADDR;
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| D | opos6ul.c | 62 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_late_init()
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| D | soc.c | 84 if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6)) in get_cpu_rev()
495 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in mmc_get_boot_dev()
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| /third_party/uboot/u-boot-2020.01/board/logicpd/imx6/ |
| D | imx6logic.c | 157 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_boot_order()
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/imx8m/ |
| D | clock_imx8mm.c | 87 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); in fracpll_configure()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/vf610/ |
| D | generic.c | 285 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcm052/ |
| D | pcm052.c | 358 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_late_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-imx8m/ |
| D | imx-regs.h | 31 #define SRC_BASE_ADDR 0x30390000 macro
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| /third_party/uboot/u-boot-2020.01/board/freescale/mx6slevk/ |
| D | mx6slevk.c | 265 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/toradex/colibri_vf/ |
| D | colibri_vf.c | 391 struct src *src = (struct src *)SRC_BASE_ADDR; in board_late_init()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcm058/ |
| D | pcm058.c | 239 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-mx6/ |
| D | imx-regs.h | 200 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) macro
486 #define src_base ((struct src *)SRC_BASE_ADDR)
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| /third_party/uboot/u-boot-2020.01/board/softing/vining_2000/ |
| D | vining_2000.c | 466 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mx6sxsabresd/ |
| D | mx6sxsabresd.c | 380 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-mx5/ |
| D | imx-regs.h | 76 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) macro
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| /third_party/uboot/u-boot-2020.01/board/el/el6x/ |
| D | el6x.c | 325 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-mx7/ |
| D | imx-regs.h | 115 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) macro
266 #define src_base ((struct src *)SRC_BASE_ADDR)
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