| /third_party/uboot/u-boot-2020.01/drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 411 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
412 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
413 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
415 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
416 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
418 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
419 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
420 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) argument
422 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
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| D | pfc-r7s72100.c | 15 #define P(bank) (0x0000 + (bank) * 4) argument
16 #define PSR(bank) (0x0100 + (bank) * 4) argument
17 #define PPR(bank) (0x0200 + (bank) * 4) argument
18 #define PM(bank) (0x0300 + (bank) * 4) argument
19 #define PMC(bank) (0x0400 + (bank) * 4) argument
20 #define PFC(bank) (0x0500 + (bank) * 4) argument
21 #define PFCE(bank) (0x0600 + (bank) * 4) argument
22 #define PNOT(bank) (0x0700 + (bank) * 4) argument
23 #define PMSR(bank) (0x0800 + (bank) * 4) argument
24 #define PMCSR(bank) (0x0900 + (bank) * 4) argument
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| /third_party/uboot/u-boot-2020.01/cmd/ |
| D | flash.c | 51 int bank, first, last; in abbrev_spec() local
58 bank = simple_strtoul (str, &ep, 10); in abbrev_spec()
60 bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || in abbrev_spec()
61 (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) in abbrev_spec()
94 ulong bank, sector_end_addr; in flash_sect_roundb() local
100 for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS && !found; ++bank) { in flash_sect_roundb()
101 info = &flash_info[bank]; in flash_sect_roundb()
193 ulong bank; in flash_fill_sect_ranges() local
198 for (bank=0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in flash_fill_sect_ranges()
199 s_first[bank] = -1; /* first sector to erase */ in flash_fill_sect_ranges()
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| /third_party/uboot/u-boot-2020.01/drivers/gpio/ |
| D | gpio-rza1.c | 13 #define P(bank) (0x0000 + (bank) * 4) argument
14 #define PSR(bank) (0x0100 + (bank) * 4) argument
15 #define PPR(bank) (0x0200 + (bank) * 4) argument
16 #define PM(bank) (0x0300 + (bank) * 4) argument
17 #define PMC(bank) (0x0400 + (bank) * 4) argument
18 #define PFC(bank) (0x0500 + (bank) * 4) argument
19 #define PFCE(bank) (0x0600 + (bank) * 4) argument
20 #define PNOT(bank) (0x0700 + (bank) * 4) argument
21 #define PMSR(bank) (0x0800 + (bank) * 4) argument
22 #define PMCSR(bank) (0x0900 + (bank) * 4) argument
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| D | omap_gpio.c | 54 static void _set_gpio_direction(const struct gpio_bank *bank, int gpio, in _set_gpio_direction() argument
57 void *reg = bank->base; in _set_gpio_direction()
74 static int _get_gpio_direction(const struct gpio_bank *bank, int gpio) in _get_gpio_direction() argument
76 void *reg = bank->base; in _get_gpio_direction()
89 static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, in _set_gpio_dataout() argument
92 void *reg = bank->base; in _set_gpio_dataout()
104 static int _get_gpio_value(const struct gpio_bank *bank, int gpio) in _get_gpio_value() argument
106 void *reg = bank->base; in _get_gpio_value()
109 input = _get_gpio_direction(bank, gpio); in _get_gpio_value()
145 const struct gpio_bank *bank; in gpio_set_value() local
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| D | intel_ich6_gpio.c | 57 static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset, in _ich6_gpio_set_value() argument
62 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
63 val = bank->lvl_write_cache; in _ich6_gpio_set_value()
65 val = inl(bank->lvl); in _ich6_gpio_set_value()
71 outl(val, bank->lvl); in _ich6_gpio_set_value()
72 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
73 bank->lvl_write_cache = val; in _ich6_gpio_set_value()
123 struct ich6_bank_priv *bank = dev_get_priv(dev); in ich6_gpio_probe() local
128 bank->use_sel = plat->base_addr; in ich6_gpio_probe()
129 bank->io_sel = plat->base_addr + 4; in ich6_gpio_probe()
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| D | s5p_gpio.c | 37 struct s5p_gpio_bank *bank; member
43 struct s5p_gpio_bank *bank; member
59 struct s5p_gpio_bank *bank; in s5p_gpio_get_bank() local
60 bank = (struct s5p_gpio_bank *)data->reg_addr; in s5p_gpio_get_bank()
61 bank += (gpio - upto) / GPIO_PER_BANK; in s5p_gpio_get_bank()
62 debug("gpio=%d, bank=%p\n", gpio, bank); in s5p_gpio_get_bank()
63 return bank; in s5p_gpio_get_bank()
73 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) in s5p_gpio_cfg_pin() argument
77 value = readl(&bank->con); in s5p_gpio_cfg_pin()
80 writel(value, &bank->con); in s5p_gpio_cfg_pin()
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| D | xilinx_gpio.c | 39 u32 bank, max_pins; in xilinx_gpio_get_bank_pin() local
43 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) { in xilinx_gpio_get_bank_pin()
44 max_pins = platdata->bank_max[bank]; in xilinx_gpio_get_bank_pin()
47 bank, pin_num); in xilinx_gpio_get_bank_pin()
48 *bank_num = bank; in xilinx_gpio_get_bank_pin()
64 u32 bank, pin; in xilinx_gpio_set_value() local
66 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev); in xilinx_gpio_set_value()
70 val = priv->output_val[bank]; in xilinx_gpio_set_value()
73 __func__, (ulong)platdata->regs, value, offset, bank, pin, val); in xilinx_gpio_set_value()
80 writel(val, &platdata->regs->gpiodata + bank * 2); in xilinx_gpio_set_value()
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| D | kona_gpio.c | 20 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) argument
21 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) argument
22 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) argument
23 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) argument
24 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) argument
25 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) argument
26 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) argument
27 #define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) argument
28 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) argument
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| D | mxs_gpio.c | 57 uint32_t bank = PAD_BANK(gpio); in gpio_get_value() local
58 uint32_t offset = PINCTRL_DIN(bank); in gpio_get_value()
67 uint32_t bank = PAD_BANK(gpio); in gpio_set_value() local
68 uint32_t offset = PINCTRL_DOUT(bank); in gpio_set_value()
80 uint32_t bank = PAD_BANK(gpio); in gpio_direction_input() local
81 uint32_t offset = PINCTRL_DOE(bank); in gpio_direction_input()
92 uint32_t bank = PAD_BANK(gpio); in gpio_direction_output() local
93 uint32_t offset = PINCTRL_DOE(bank); in gpio_direction_output()
119 unsigned bank, pin; in name_to_gpio() local
122 bank = simple_strtoul(name, &end, 10); in name_to_gpio()
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| D | da8xx_gpio.c | 345 static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio) in _gpio_direction_input() argument
347 setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); in _gpio_direction_input()
351 static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio) in _gpio_get_value() argument
354 ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio)); in _gpio_get_value()
358 static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value) in _gpio_set_value() argument
361 bank->set_data = 1U << GPIO_BIT(gpio); in _gpio_set_value()
363 bank->clr_data = 1U << GPIO_BIT(gpio); in _gpio_set_value()
368 static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio) in _gpio_get_dir() argument
370 return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio)); in _gpio_get_dir()
373 static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio, in _gpio_direction_output() argument
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| /third_party/uboot/u-boot-2020.01/arch/powerpc/cpu/mpc85xx/ |
| D | fsl_corenet_serdes.c | 64 int bank; member
104 return lanes[lane].bank; in serdes_get_bank_by_lane()
112 int bank = lanes[lane].bank; in serdes_lane_enabled() local
116 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
125 if (bank > 0) in serdes_lane_enabled()
126 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
283 static void enable_bank(ccsr_gur_t *gur, int bank) in enable_bank() argument
286 u32 temp_lpd_b = srds_lpd_b[bank]; in enable_bank()
300 if (bank == FSL_SRDS_BANK_2) { in enable_bank()
303 } else if (bank == FSL_SRDS_BANK_3) { in enable_bank()
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| /third_party/uboot/u-boot-2020.01/drivers/pinctrl/rockchip/ |
| D | pinctrl-rockchip-core.c | 19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
38 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
41 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux()
48 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
61 bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
64 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_mux_route()
71 if (data->bank_num == bank->bank_num && in rockchip_get_mux_route()
111 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
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| D | pinctrl-rv1108.c | 78 static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rv1108_set_mux() argument
80 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_set_mux()
87 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rv1108_set_mux()
91 mux_type = bank->iomux[iomux_num].type; in rv1108_set_mux()
92 reg = bank->iomux[iomux_num].offset; in rv1108_set_mux()
95 if (bank->recalced_mask & BIT(pin)) in rv1108_set_mux()
96 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rv1108_set_mux()
108 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_pull_reg_and_bit() argument
112 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_pull_reg_and_bit()
115 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
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| D | pinctrl-rk3288.c | 31 static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3288_set_mux() argument
33 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_set_mux()
40 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3288_set_mux()
44 mux_type = bank->iomux[iomux_num].type; in rk3288_set_mux()
45 reg = bank->iomux[iomux_num].offset; in rk3288_set_mux()
48 if (bank->route_mask & BIT(pin)) { in rk3288_set_mux()
49 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, in rk3288_set_mux()
58 if (bank->bank_num == 0) { in rk3288_set_mux()
75 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_pull_reg_and_bit() argument
79 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_calc_pull_reg_and_bit()
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| D | pinctrl-rk3399.c | 53 static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3399_set_mux() argument
55 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_set_mux()
62 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3399_set_mux()
66 mux_type = bank->iomux[iomux_num].type; in rk3399_set_mux()
67 reg = bank->iomux[iomux_num].offset; in rk3399_set_mux()
70 if (bank->route_mask & BIT(pin)) { in rk3399_set_mux()
71 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, in rk3399_set_mux()
89 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_pull_reg_and_bit() argument
93 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_pull_reg_and_bit()
96 if (bank->bank_num == 0 || bank->bank_num == 1) { in rk3399_calc_pull_reg_and_bit()
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| D | pinctrl-rk3368.c | 14 static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3368_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_set_mux()
23 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3368_set_mux()
27 mux_type = bank->iomux[iomux_num].type; in rk3368_set_mux()
28 reg = bank->iomux[iomux_num].offset; in rk3368_set_mux()
41 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_pull_reg_and_bit() argument
45 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_pull_reg_and_bit()
48 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
57 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
66 static int rk3368_set_pull(struct rockchip_pin_bank *bank, in rk3368_set_pull() argument
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| D | pinctrl-rk3328.c | 124 static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3328_set_mux() argument
126 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3328_set_mux()
133 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3328_set_mux()
137 mux_type = bank->iomux[iomux_num].type; in rk3328_set_mux()
138 reg = bank->iomux[iomux_num].offset; in rk3328_set_mux()
141 if (bank->recalced_mask & BIT(pin)) in rk3328_set_mux()
142 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rk3328_set_mux()
144 if (bank->route_mask & BIT(pin)) { in rk3328_set_mux()
145 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, in rk3328_set_mux()
162 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3328_calc_pull_reg_and_bit() argument
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| D | pinctrl-px30.c | 74 static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in px30_set_mux() argument
76 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_set_mux()
83 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in px30_set_mux()
87 mux_type = bank->iomux[iomux_num].type; in px30_set_mux()
88 reg = bank->iomux[iomux_num].offset; in px30_set_mux()
91 if (bank->route_mask & BIT(pin)) { in px30_set_mux()
92 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, in px30_set_mux()
113 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_pull_reg_and_bit() argument
117 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_pull_reg_and_bit()
120 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
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| /third_party/uboot/u-boot-2020.01/drivers/misc/ |
| D | mxc_ocotp.c | 135 u32 fuse_word_physical(u32 bank, u32 word_index) in fuse_word_physical() argument
138 if (bank == 8) in fuse_word_physical()
150 u32 fuse_word_physical(u32 bank, u32 word_index) in fuse_word_physical() argument
168 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, in prepare_access() argument
173 if (bank >= FUSE_BANKS || in prepare_access()
174 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || in prepare_access()
181 if ((bank == 7 || bank == 8) && in prepare_access()
182 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { in prepare_access()
215 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, in prepare_read() argument
218 return prepare_access(regs, bank, word, val != NULL, caller); in prepare_read()
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| D | fsl_iim.c | 93 } bank[8]; member
100 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, in prepare_access() argument
105 if (bank >= ARRAY_SIZE((*regs)->bank) || in prepare_access()
106 word >= ARRAY_SIZE((*regs)->bank[0].word) || in prepare_access()
128 static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val, in prepare_read() argument
133 ret = prepare_access(regs, bank, word, val != NULL, caller); in prepare_read()
142 int fuse_read(u32 bank, u32 word, u32 *val) in fuse_read() argument
148 ret = prepare_read(®s, bank, word, val, __func__); in fuse_read()
152 *val = iim_read32(®s->bank[bank].word[word]); in fuse_read()
163 static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit, in direct_access() argument
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-tegra/ |
| D | cboot.c | 223 static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end) in mark_ram_allocated() argument
225 u64 bank_start = tegra_mem_map[bank].virt; in mark_ram_allocated()
226 u64 bank_size = tegra_mem_map[bank].size; in mark_ram_allocated()
242 memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank], in mark_ram_allocated()
243 CONFIG_NR_DRAM_BANKS - bank - 1); in mark_ram_allocated()
244 tegra_mem_map[bank].size = allocated_start - bank_start; in mark_ram_allocated()
245 bank++; in mark_ram_allocated()
246 tegra_mem_map[bank].virt = allocated_end; in mark_ram_allocated()
247 tegra_mem_map[bank].phys = allocated_end; in mark_ram_allocated()
248 tegra_mem_map[bank].size = bank_end - allocated_end; in mark_ram_allocated()
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| /third_party/uboot/u-boot-2020.01/drivers/mtd/spi/hifmc100/ |
| D | hifmc100_spi_s25fl256s.c | 69 unsigned char bank; in spi_s25fl256s_entry_4addr() local
82 bank = spi_general_get_flash_register(spi, SS_SPI_CMD_BRRD); in spi_s25fl256s_entry_4addr()
84 bank); in spi_s25fl256s_entry_4addr()
85 if (ss_spi_nor_get_eae_by_br(bank) == enable) { in spi_s25fl256s_entry_4addr()
87 bank); in spi_s25fl256s_entry_4addr()
93 bank |= SS_SPI_NOR_BR_EAE_MASK; in spi_s25fl256s_entry_4addr()
95 bank &= ~SS_SPI_NOR_BR_EAE_MASK; in spi_s25fl256s_entry_4addr()
96 writeb(bank, host->iobase); in spi_s25fl256s_entry_4addr()
105 bank = spi_general_get_flash_register(spi, SS_SPI_CMD_BRRD); in spi_s25fl256s_entry_4addr()
107 bank); in spi_s25fl256s_entry_4addr()
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| /third_party/uboot/u-boot-2020.01/drivers/pinctrl/ |
| D | pinctrl-sti.c | 47 unsigned char bank; member
61 int bank = pin_desc->bank; in sti_alternate_select() local
66 switch (bank) { in sti_alternate_select()
68 sysconfreg += bank; in sti_alternate_select()
71 sysconfreg += bank - 10; in sti_alternate_select()
74 sysconfreg += bank - 30; in sti_alternate_select()
77 sysconfreg += bank - 40; in sti_alternate_select()
96 int bank = pin_desc->bank; in sti_pin_configure() local
150 switch (bank) { in sti_pin_configure()
152 sysconfreg += bank / 4; in sti_pin_configure()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | fsl_lsch2_serdes.c | 200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
203 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
206 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
208 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
216 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
219 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
222 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
224 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
263 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
265 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
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