| /third_party/uboot/u-boot-2020.01/arch/arm/dts/ |
| D | imx6sx.dtsi | 78 clocks = <&clks IMX6SX_CLK_ARM>,
79 <&clks IMX6SX_CLK_PLL2_PFD2>,
80 <&clks IMX6SX_CLK_STEP>,
81 <&clks IMX6SX_CLK_PLL1_SW>,
82 <&clks IMX6SX_CLK_PLL1_SYS>;
151 clocks = <&clks IMX6SX_CLK_OCRAM>;
168 clocks = <&clks IMX6SX_CLK_GPU>,
169 <&clks IMX6SX_CLK_GPU>,
170 <&clks IMX6SX_CLK_GPU>;
184 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
[all …]
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| D | imx6sll.dtsi | 67 clocks = <&clks IMX6SLL_CLK_ARM>,
68 <&clks IMX6SLL_CLK_PLL2_PFD2>,
69 <&clks IMX6SLL_CLK_STEP>,
70 <&clks IMX6SLL_CLK_PLL1_SW>,
71 <&clks IMX6SLL_CLK_PLL1_SYS>,
72 <&clks IMX6SLL_CLK_PLL1>,
73 <&clks IMX6SLL_PLL1_BYPASS>,
74 <&clks IMX6SLL_PLL1_BYPASS_SRC>;
136 clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
137 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
[all …]
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| D | imx6qdl.dtsi | 79 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
159 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
170 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
171 <&clks IMX6QDL_CLK_GPMI_APB>,
172 <&clks IMX6QDL_CLK_GPMI_BCH>,
173 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
174 <&clks IMX6QDL_CLK_PER1_BCH>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
214 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
[all …]
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| D | imx6ul.dtsi | 81 clocks = <&clks IMX6UL_CLK_ARM>,
82 <&clks IMX6UL_CLK_PLL2_BUS>,
83 <&clks IMX6UL_CLK_PLL2_PFD2>,
84 <&clks IMX6UL_CA7_SECONDARY_SEL>,
85 <&clks IMX6UL_CLK_STEP>,
86 <&clks IMX6UL_CLK_PLL1_SW>,
87 <&clks IMX6UL_CLK_PLL1_SYS>;
155 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
186 clocks = <&clks IMX6UL_CLK_APBHDMA>;
197 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
[all …]
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| D | imx53.dtsi | 56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
[all …]
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| D | imx7ulp.dtsi | 163 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
197 clocks = <&clks IMX7ULP_CLK_SNVS>;
205 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
213 clocks = <&clks IMX7ULP_CLK_LPIT1>;
215 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
216 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
225 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
226 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
[all …]
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| D | imx6qp.dtsi | 12 clocks = <&clks IMX6QDL_CLK_OCRAM>;
18 clocks = <&clks IMX6QDL_CLK_OCRAM>;
26 clocks = <&clks IMX6QDL_CLK_PRE0>;
35 clocks = <&clks IMX6QDL_CLK_PRE1>;
44 clocks = <&clks IMX6QDL_CLK_PRE2>;
53 clocks = <&clks IMX6QDL_CLK_PRE3>;
61 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
62 <&clks IMX6QDL_CLK_PRG0_AXI>;
70 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
71 <&clks IMX6QDL_CLK_PRG1_AXI>;
[all …]
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| D | imx6q.dtsi | 43 clocks = <&clks IMX6QDL_CLK_ARM>,
44 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
45 <&clks IMX6QDL_CLK_STEP>,
46 <&clks IMX6QDL_CLK_PLL1_SW>,
47 <&clks IMX6QDL_CLK_PLL1_SYS>;
77 clocks = <&clks IMX6QDL_CLK_ARM>,
78 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
79 <&clks IMX6QDL_CLK_STEP>,
80 <&clks IMX6QDL_CLK_PLL1_SW>,
81 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
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| D | imx6sl.dtsi | 68 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
69 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
70 <&clks IMX6SL_CLK_PLL1_SYS>;
115 clocks = <&clks IMX6SL_CLK_OCRAM>;
155 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
156 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
157 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
158 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
159 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
174 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
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| D | imx7s.dtsi | 102 clocks = <&clks IMX7D_CLK_ARM>;
122 clocks = <&clks IMX7D_USB_PHY1_CLK>;
129 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
196 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
228 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
241 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
278 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
305 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
319 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
437 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
[all …]
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| D | imx6dl.dtsi | 37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
67 clocks = <&clks IMX6QDL_CLK_ARM>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
69 <&clks IMX6QDL_CLK_STEP>,
70 <&clks IMX6QDL_CLK_PLL1_SW>,
71 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
|
| D | imx6q-logicpd.dts | 60 &clks {
61 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
62 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
63 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
64 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
65 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
66 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
67 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
|
| D | imx7d-pico.dtsi | 70 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
75 &clks {
76 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
77 <&clks IMX7D_CLKO2_ROOT_DIV>;
78 assigned-clock-parents = <&clks IMX7D_CKIL>;
92 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
93 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
94 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
237 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
238 <&clks IMX7D_SAI1_ROOT_CLK>;
[all …]
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| D | imx7s-warp.dts | 78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
83 &clks {
84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
208 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
225 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
226 <&clks IMX7D_SAI1_ROOT_CLK>;
227 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
235 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
236 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
243 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
[all …]
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| D | imx7d.dtsi | 77 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
94 clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
106 clocks = <&clks IMX7D_USB_CTRL_CLK>;
121 clocks = <&clks IMX7D_USB_PHY2_CLK>;
131 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
132 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
133 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
134 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
135 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
| D | imx28.dtsi | 94 clocks = <&clks 25>;
111 clocks = <&clks 50>;
123 clocks = <&clks 46>;
134 clocks = <&clks 47>;
145 clocks = <&clks 48>;
156 clocks = <&clks 49>;
998 clocks = <&clks 26>;
1019 clocks = <&clks 25>;
1031 clocks = <&clks 55>;
1041 clocks = <&clks 58>, <&clks 58>;
[all …]
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| D | imx7d-meerkat96.dts | 143 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
144 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
151 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
152 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
160 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
161 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
168 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
169 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
| D | imx6ul-14x14-evk.dtsi | 79 &clks {
80 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
120 clocks = <&clks IMX6UL_CLK_ENET_REF>;
127 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
163 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
164 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
202 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
203 <&clks IMX6UL_CLK_SAI2>;
204 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
| /third_party/uboot/u-boot-2020.01/drivers/clk/altera/ |
| D | clk-arria10.c | 25 struct clk_bulk clks; member
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
77 *upclk = &plat->clks.clks[reg]; in socfpga_a10_clk_get_upstream()
191 struct clk_bulk *bulk = &plat->clks; in socfpga_a10_handoff_workaround()
215 bulk->clks = devm_kcalloc(dev, bulk->count, in socfpga_a10_handoff_workaround()
217 if (!bulk->clks) in socfpga_a10_handoff_workaround()
220 ret = clk_request(dev, &bulk->clks[0]); in socfpga_a10_handoff_workaround()
222 free(bulk->clks); in socfpga_a10_handoff_workaround()
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 54 const struct clk_periph *clks; member
246 const struct clk_periph *clk = &priv->clks[id]; in get_parent_rate()
303 const struct clk_periph *clk = &priv->clks[id]; in periph_clk_get_rate()
335 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in periph_clk_enable()
389 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in armada_37xx_periph_clk_set_rate()
437 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in armada_37xx_periph_clk_set_parent()
470 const struct clk_periph *clks; in armada_37xx_periph_clk_dump() local
476 clks = priv->clks; in armada_37xx_periph_clk_dump()
479 printf(" %s at %lu Hz\n", clks[i].name, in armada_37xx_periph_clk_dump()
522 const struct clk_periph *clks; in armada_37xx_periph_clk_probe() local
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/usb/host/ |
| D | dwc3-of-simple.c | 20 struct clk_bulk clks; member
49 ret = clk_get_bulk(dev, &simple->clks); in dwc3_of_simple_clk_init()
56 ret = clk_enable_bulk(&simple->clks); in dwc3_of_simple_clk_init()
58 clk_release_bulk(&simple->clks); in dwc3_of_simple_clk_init()
88 clk_release_bulk(&simple->clks); in dwc3_of_simple_remove()
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/fsl/ |
| D | util.c | 87 unsigned long long clks, clks_rem; in picos_to_mclk() local
95 clks = picos * (unsigned long long)data_rate; in picos_to_mclk()
100 clks_rem = do_div(clks, UL_5POW12); in picos_to_mclk()
101 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; in picos_to_mclk()
102 clks >>= 13; in picos_to_mclk()
106 clks++; in picos_to_mclk()
109 if (clks > ULL_8FS) in picos_to_mclk()
110 clks = ULL_8FS; in picos_to_mclk()
111 return (unsigned int) clks; in picos_to_mclk()
|
| /third_party/ltp/testcases/kernel/syscalls/timerfd/ |
| D | timerfd01.c | 85 struct tcase *clks = &tcases[n]; in run() local
87 tst_res(TINFO, "testing %s", clks->name); in run()
89 tfd = SAFE_TIMERFD_CREATE(clks->id, 0); in run()
96 tnow = getustime(clks->id); in run()
101 tnow = getustime(clks->id); in run()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/mach-rockchip/rk3288/ |
| D | rk3288.c | 160 } clks[] = { in do_clock() local
181 for (i = 0; i < ARRAY_SIZE(clks); i++) { in do_clock()
185 clk.id = clks[i].id; in do_clock()
191 printf("%s: %lu\n", clks[i].name, rate); in do_clock()
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| /third_party/uboot/u-boot-2020.01/drivers/power/domain/ |
| D | meson-gx-pwrc-vpu.c | 40 struct clk_bulk clks; member
93 ret = clk_enable_bulk(&priv->clks); in meson_gx_pwrc_vpu_on()
146 ret = clk_enable_bulk(&priv->clks); in meson_g12a_pwrc_vpu_on()
198 clk_disable_bulk(&priv->clks); in meson_gx_pwrc_vpu_off()
239 clk_disable_bulk(&priv->clks); in meson_g12a_pwrc_vpu_off()
319 ret = clk_get_bulk(dev, &priv->clks); in meson_gx_pwrc_vpu_probe()
|