| /third_party/uboot/u-boot-2020.01/arch/arm/mach-omap2/omap3/ |
| D | sys_info.c | 245 char *cpu_family_s, *cpu_s, *sec_s, *max_clk; in print_cpuinfo() local
269 max_clk = "720 MHz"; in print_cpuinfo()
271 max_clk = "600 MHz"; in print_cpuinfo()
287 max_clk = "600 MHz"; in print_cpuinfo()
294 max_clk = "800 MHz"; in print_cpuinfo()
299 max_clk = "1 GHz"; in print_cpuinfo()
304 max_clk = "800 MHz"; in print_cpuinfo()
309 max_clk = "1 GHz"; in print_cpuinfo()
314 max_clk = "800 MHz"; in print_cpuinfo()
319 max_clk = "1 GHz"; in print_cpuinfo()
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/mmc/ |
| D | atmel_sdhci.c | 21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; in atmel_sdhci_init() local
32 max_clk = at91_get_periph_generated_clk(id); in atmel_sdhci_init()
33 if (!max_clk) { in atmel_sdhci_init()
38 host->max_clk = max_clk; in atmel_sdhci_init()
59 u32 max_clk; in atmel_sdhci_probe() local
86 max_clk = clk_get_rate(&clk); in atmel_sdhci_probe()
87 if (!max_clk) in atmel_sdhci_probe()
90 host->max_clk = max_clk; in atmel_sdhci_probe()
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| D | kona_sdhci.c | 80 u32 max_clk; in kona_sdhci_init() local
93 &max_clk); in kona_sdhci_init()
98 &max_clk); in kona_sdhci_init()
103 &max_clk); in kona_sdhci_init()
108 &max_clk); in kona_sdhci_init()
123 host->max_clk = max_clk; in kona_sdhci_init()
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| D | aspeed_sdhci.c | 23 u32 max_clk; in aspeed_sdhci_probe() local
38 max_clk = clk_get_rate(&clk); in aspeed_sdhci_probe()
39 if (IS_ERR_VALUE(max_clk)) { in aspeed_sdhci_probe()
40 ret = max_clk; in aspeed_sdhci_probe()
44 host->max_clk = max_clk; in aspeed_sdhci_probe()
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| D | mv_sdhci.c | 71 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) in mv_sdh_init() argument
83 host->max_clk = max_clk; in mv_sdh_init()
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| D | sdhci.c | 555 if ((host->max_clk / div) <= clock)
567 if (host->max_clk <= clock) {
573 if ((host->max_clk / div) <= clock)
582 if ((host->max_clk / div) <= clock)
902 if (host->max_clk == 0) {
904 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
907 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
909 host->max_clk *= 1000000;
911 host->max_clk *= host->clk_mul;
913 if (host->max_clk == 0) {
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| D | bcm2835_sdhost.c | 164 unsigned int max_clk; /* Max possible freq */ member
628 div = host->max_clk / clock; in bcm2835_set_clock()
631 if ((host->max_clk / div) > clock) in bcm2835_set_clock()
638 clock = host->max_clk / (div + 2); in bcm2835_set_clock()
733 cfg->f_max = host->max_clk; in bcm2835_add_host()
734 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; in bcm2835_add_host()
773 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); in bcm2835_probe()
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| D | dw_mmc.c | 583 u32 max_clk, u32 min_clk) argument
590 cfg->f_max = max_clk;
614 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) argument
616 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
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| D | pic32_sdhci.c | 58 host->max_clk = f_min_max[1]; in pic32_sdhci_probe()
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| D | rockchip_sdhci.c | 62 host->max_clk = max_frequency; in arasan_sdhci_probe()
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| D | msm_sdhci.c | 98 host->max_clk = 0; in msm_sdc_probe()
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| D | ftsdc010_mci.c | 372 uint caps, u32 max_clk, u32 min_clk) in ftsdc_setup_cfg() argument
376 cfg->f_max = max_clk; in ftsdc_setup_cfg()
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| D | s5p_sdhci.c | 93 host->max_clk = 52000000; in s5p_sdhci_core_init()
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| D | bcm2835_sdhci.c | 215 host->max_clk = emmc_freq; in bcm2835_sdhci_probe()
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| D | himci.c | 1232 unsigned int max_clk, unsigned int min_clk) in himci_setup_cfg() argument
1236 cfg->f_max = max_clk; in himci_setup_cfg()
1247 int add_himci(struct himci_host *host, unsigned int max_clk, unsigned int min_clk) in add_himci() argument
1249 himci_setup_cfg(&host->cfg, host, max_clk, min_clk); in add_himci()
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| D | iproc_sdhci.c | 203 host->max_clk = f_min_max[1]; in iproc_sdhci_probe()
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| D | zynq_sdhci.c | 243 host->max_clk = clock; in arasan_sdhci_probe()
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| D | am654_sdhci.c | 238 host->max_clk = clock; in am654_sdhci_probe()
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| /third_party/uboot/u-boot-2020.01/include/ |
| D | dwmmc.h | 270 u32 max_clk, u32 min_clk);
300 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
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| D | sdhci.h | 345 unsigned int max_clk; /* Maximum Base Clock frequency */ member
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-mvebu/include/mach/ |
| D | cpu.h | 148 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
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| /third_party/uboot/u-boot-2020.01/product/hiosd/vo/arch/comm/src/ |
| D | drv_vo_dev_comm.c | 272 hi_u32 max_clk; in vo_drv_check_dev_pll_foutvco() local
285 max_clk = vo_drv_dev_get_max_clk(dev); in vo_drv_check_dev_pll_foutvco()
286 if (pixel_clk > max_clk) { in vo_drv_check_dev_pll_foutvco()
289 … pll->post_div1, pll->post_div2, sync_info->pre_div, sync_info->dev_div, pixel_clk, max_clk); in vo_drv_check_dev_pll_foutvco()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/vo/arch/hi3531dv200/hal/ |
| D | drv_vo_dev.c | 971 hi_u32 max_clk; in vo_drv_dev_get_max_clk() local
973 max_clk = (dev == VO_DEV_DHD0) ? VO_PLL_MAX_CLK_594000 : VO_PLL_MAX_CLK_297000; in vo_drv_dev_get_max_clk()
974 return max_clk; in vo_drv_dev_get_max_clk()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/vo/arch/hi3535av100/hal/ |
| D | drv_vo_dev.c | 970 hi_u32 max_clk; in vo_drv_dev_get_max_clk() local
972 max_clk = (dev == VO_DEV_DHD0) ? VO_PLL_MAX_CLK_297000 : VO_PLL_MAX_CLK_148500; in vo_drv_dev_get_max_clk()
973 return max_clk; in vo_drv_dev_get_max_clk()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/vo/arch/hi3521dv200/hal/ |
| D | drv_vo_dev.c | 1246 hi_u32 max_clk; in vo_drv_dev_get_max_clk() local
1248 max_clk = (dev == VO_DEV_DHD0) ? VO_PLL_MAX_CLK_297000 : VO_PLL_MAX_CLK_148500; in vo_drv_dev_get_max_clk()
1249 return max_clk; in vo_drv_dev_get_max_clk()
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