| /third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/axp/ |
| D | ddr3_dfs.c | 70 u32 reg; in wait_refresh_op_complete() local
74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
116 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
134 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
143 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
145 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
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| D | ddr3_write_leveling.c | 66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
75 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
76 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
79 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
83 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
85 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
89 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/phy/hibvt/ |
| D | phy_usb_hi3531dv200.c | 51 unsigned int reg; in usb2_crg_config() local
54 reg = readl(USB2_CTRL1_CFG); in usb2_crg_config()
55 reg |= USB2_1_SRST_REQ; in usb2_crg_config()
56 writel(reg, USB2_CTRL1_CFG); in usb2_crg_config()
60 reg = readl(USB2_PHY1_CFG); in usb2_crg_config()
61 reg |= (USB2_PHY1_REQ | USB2_PHY1_TREQ | USB2_PHY1_APB_SRST_REQ); in usb2_crg_config()
62 writel(reg, USB2_PHY1_CFG); in usb2_crg_config()
66 reg = readl(USB2_PHY1_CFG); in usb2_crg_config()
67 reg |= USB2_PHY1_XTAL_CKEN; in usb2_crg_config()
68 writel(reg, USB2_PHY1_CFG); in usb2_crg_config()
[all …]
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| D | phy_usb_hi3521dv200.c | 46 unsigned int reg; in usb2_phy0_config() local
50 reg = readl(USB2_PHY0_BASE + PHY_PLL_OFFSET); in usb2_phy0_config()
51 reg |= PHY_PLL_ENABLE; in usb2_phy0_config()
52 writel(reg, USB2_PHY0_BASE + PHY_PLL_OFFSET); in usb2_phy0_config()
59 reg = readl(USB2_PHY0_BASE + U2_ANA_CFG2); in usb2_phy0_config()
60 reg = usb2_rt_trim_clr(reg); in usb2_phy0_config()
61 reg |= usb2_rt_trim_set(trim_val); in usb2_phy0_config()
62 writel(reg, USB2_PHY0_BASE + U2_ANA_CFG2); in usb2_phy0_config()
67 reg = readl(USB2_PHY0_BASE + RG_HSTX_MBIAS); in usb2_phy0_config()
68 reg &= ~RG_HSTX_MBIAS_MASK; in usb2_phy0_config()
[all …]
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| D | phy-usb-hi3519av100.c | 109 unsigned int reg; in hisi_usb_eye_config() local
113 reg = readl(MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
114 reg &= ~USB2_PHY0_TXVREFTUNE; in hisi_usb_eye_config()
115 reg &= ~USB2_PHY0_TXPRE; in hisi_usb_eye_config()
116 reg |= USB2_PHY0_VREF_VAL; in hisi_usb_eye_config()
117 reg |= USB2_PHY0_PRE_VAL; in hisi_usb_eye_config()
118 writel(reg, MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
123 reg = readl(MISC_REG_BASE + USB2_PHY1); in hisi_usb_eye_config()
124 reg &= ~USB2_PHY1_TXVREFTUNE; in hisi_usb_eye_config()
125 reg &= ~USB2_PHY1_TXPRE; in hisi_usb_eye_config()
[all …]
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| D | phy-usb-hi3556av100.c | 109 unsigned int reg; in hisi_usb_eye_config() local
113 reg = readl(MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
114 reg &= ~USB2_PHY0_TXVREFTUNE; in hisi_usb_eye_config()
115 reg &= ~USB2_PHY0_TXPRE; in hisi_usb_eye_config()
116 reg |= USB2_PHY0_VREF_VAL; in hisi_usb_eye_config()
117 reg |= USB2_PHY0_PRE_VAL; in hisi_usb_eye_config()
118 writel(reg, MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
123 reg = readl(MISC_REG_BASE + USB2_PHY1); in hisi_usb_eye_config()
124 reg &= ~USB2_PHY1_TXVREFTUNE; in hisi_usb_eye_config()
125 reg &= ~USB2_PHY1_TXPRE; in hisi_usb_eye_config()
[all …]
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| D | phy-hi3516dv200-usb.c | 124 unsigned int reg; in usb2_eye_config() local
126 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
127 reg &= ~HIXVP_PHY_PRE_DRIVE_MASK; in usb2_eye_config()
128 reg |= HIXVP_PHY_PRE_DRIVE_VAL; in usb2_eye_config()
129 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
132 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
133 reg |= HIXVP_PHY_TX_TEST_BIT; in usb2_eye_config()
134 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
137 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
138 reg &= ~HIXVP_PHY_DISCONNECT_REFERENCE_MASK; in usb2_eye_config()
[all …]
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| D | phy-hi3518ev300-usb.c | 125 unsigned int reg; in usb2_eye_config() local
127 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
128 reg &= ~HIXVP_PHY_PRE_DRIVE_MASK; in usb2_eye_config()
129 reg |= HIXVP_PHY_PRE_DRIVE_VAL; in usb2_eye_config()
130 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
133 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
134 reg |= HIXVP_PHY_TX_TEST_BIT; in usb2_eye_config()
135 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
138 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
139 reg &= ~HIXVP_PHY_DISCONNECT_REFERENCE_MASK; in usb2_eye_config()
[all …]
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| D | phy-hi3516ev300-usb.c | 126 unsigned int reg; in usb2_eye_config() local
128 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
129 reg &= ~HIXVP_PHY_PRE_DRIVE_MASK; in usb2_eye_config()
130 reg |= HIXVP_PHY_PRE_DRIVE_VAL; in usb2_eye_config()
131 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
134 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
135 reg |= HIXVP_PHY_TX_TEST_BIT; in usb2_eye_config()
136 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
139 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
140 reg &= ~HIXVP_PHY_DISCONNECT_REFERENCE_MASK; in usb2_eye_config()
[all …]
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| D | phy-hi3516ev200-usb.c | 124 unsigned int reg; in usb2_eye_config() local
126 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
127 reg &= ~HIXVP_PHY_PRE_DRIVE_MASK; in usb2_eye_config()
128 reg |= HIXVP_PHY_PRE_DRIVE_VAL; in usb2_eye_config()
129 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
132 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
133 reg |= HIXVP_PHY_TX_TEST_BIT; in usb2_eye_config()
134 writel(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
137 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
138 reg &= ~HIXVP_PHY_DISCONNECT_REFERENCE_MASK; in usb2_eye_config()
[all …]
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| D | phy-usb-hi3516dv300.c | 102 unsigned int reg; in usb2_eye_config() local
105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
106 reg &= ~HS_HIGH_HEIGHT_TUNING_MASK; in usb2_eye_config()
107 reg |= HS_HIGH_HEIGHT_TUNING_VAL; in usb2_eye_config()
108 writel(reg, USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
112 reg &= ~PRE_EMPHASIS_TUNING_MASK; in usb2_eye_config()
113 reg |= PRE_EMPHASIS_TUNING_VAL; in usb2_eye_config()
114 writel(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
[all …]
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| D | phy-usb-hi3556v200.c | 102 unsigned int reg; in usb2_eye_config() local
105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
106 reg &= ~HS_HIGH_HEIGHT_TUNING_MASK; in usb2_eye_config()
107 reg |= HS_HIGH_HEIGHT_TUNING_VAL; in usb2_eye_config()
108 writel(reg, USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
112 reg &= ~PRE_EMPHASIS_TUNING_MASK; in usb2_eye_config()
113 reg |= PRE_EMPHASIS_TUNING_VAL; in usb2_eye_config()
114 writel(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
[all …]
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| D | phy-usb-hi3559v200.c | 102 unsigned int reg; in usb2_eye_config() local
105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
106 reg &= ~HS_HIGH_HEIGHT_TUNING_MASK; in usb2_eye_config()
107 reg |= HS_HIGH_HEIGHT_TUNING_VAL; in usb2_eye_config()
108 writel(reg, USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
112 reg &= ~PRE_EMPHASIS_TUNING_MASK; in usb2_eye_config()
113 reg |= PRE_EMPHASIS_TUNING_VAL; in usb2_eye_config()
114 writel(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
[all …]
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| D | phy-usb-hi3516cv500.c | 102 unsigned int reg; in usb2_eye_config() local
105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
106 reg &= ~HS_HIGH_HEIGHT_TUNING_MASK; in usb2_eye_config()
107 reg |= HS_HIGH_HEIGHT_TUNING_VAL; in usb2_eye_config()
108 writel(reg, USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
112 reg &= ~PRE_EMPHASIS_TUNING_MASK; in usb2_eye_config()
113 reg |= PRE_EMPHASIS_TUNING_VAL; in usb2_eye_config()
114 writel(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
[all …]
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| D | phy-usb-hi3559av100.c | 68 int reg; in usb3_eye_config() local
71 reg = readl(MISC_REG_BASE + USB2_PHY0_CTRL); in usb3_eye_config()
72 reg &= ~USB2_PHY_MASK; in usb3_eye_config()
73 reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */ in usb3_eye_config()
74 reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */ in usb3_eye_config()
75 writel(reg, MISC_REG_BASE + USB2_PHY0_CTRL); in usb3_eye_config()
79 reg = readl(MISC_REG_BASE + USB2_PHY1_CTRL); in usb3_eye_config()
80 reg &= ~USB2_PHY_MASK; in usb3_eye_config()
81 reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */ in usb3_eye_config()
82 reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */ in usb3_eye_config()
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/video/exynos/ |
| D | exynos_dp_lowlevel.c | 22 unsigned int reg; in exynos_dp_enable_video_input() local
24 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
25 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
29 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
31 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
39 unsigned int reg; in exynos_dp_enable_video_bist() local
41 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
42 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
46 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
48 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
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| D | exynos_mipi_dsi_lowlevel.c | 20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
29 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
44 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/dts/ |
| D | armada-38x-controlcenterdc.dts | 59 reg = <0x00000000 0x10000000>; /* 256 MB */
81 reg = <0x21>;
88 reg = <0x22>;
94 reg = <0x23>;
100 reg = <0x24>;
106 reg = <0x25>;
112 reg = <0x26>;
123 reg = <0x29>;
130 reg = <0x2d>;
132 reg = <0>;
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/mmc/ |
| D | hisi_hi3559av100.c | 109 unsigned int reg; in hisi_dll_reset_assert() local
112 reg = readl(crg_addr); in hisi_dll_reset_assert()
113 reg |= SDIO_DRV_DLL_SRST_REQ | SDIO_SAMPL_DLL_SRST_REQ; in hisi_dll_reset_assert()
114 writel(reg, crg_addr); in hisi_dll_reset_assert()
120 unsigned int reg; in hisi_dll_reset_deassert() local
123 reg = readl(crg_addr); in hisi_dll_reset_deassert()
124 reg &= ~(SDIO_DRV_DLL_SRST_REQ | SDIO_SAMPL_DLL_SRST_REQ); in hisi_dll_reset_deassert()
125 writel(reg, crg_addr); in hisi_dll_reset_deassert()
131 unsigned int sel, reg; in hisi_set_crg() local
138 reg = readl(crg_addr); in hisi_set_crg()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-tegra/tegra20/ |
| D | warmboot_avp.c | 34 u32 reg; in wb_start() local
42 : "=r"(reg) /* output */ in wb_start()
46 if (reg != NV_WB_RUN_ADDRESS) in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
56 reg |= SWR_CSITE_RST; in wb_start()
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
68 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
76 reg |= CPU_CLMP; in wb_start()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | fsl_lsch2_serdes.c | 150 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
181 reg &= 0xFF9FFFFF; in setup_serdes_volt()
182 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
191 reg &= 0xFF9FFFFF; in setup_serdes_volt()
192 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
201 reg &= 0xFFFFFFBF; in setup_serdes_volt()
202 reg |= 0x10000000; in setup_serdes_volt()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/ |
| D | clock.c | 29 u32 reg; in enable_ocotp_clk() local
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
33 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
35 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
83 u32 reg; in enable_usboh3_clk() local
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
87 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
89 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
90 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/mips/dts/ |
| D | jr2_pcb111.dts | 49 reg = <0>; /* CS0 */
81 reg = <0>;
84 reg = <1>;
87 reg = <2>;
90 reg = <3>;
93 reg = <4>;
96 reg = <5>;
99 reg = <6>;
102 reg = <7>;
105 reg = <8>;
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/mtd/nand/raw/hifmc100/ |
| D | hifmc100_spi_general.c | 30 unsigned int reg; in spi_nand_set_cmd() local
32 reg = fmc_cmd_cmd1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES); in spi_nand_set_cmd()
33 hifmc_write(host, FMC_CMD, reg); in spi_nand_set_cmd()
34 fmc_pr(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg); in spi_nand_set_cmd()
39 reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN | in spi_nand_set_cmd()
41 hifmc_write(host, FMC_OP_CFG, reg); in spi_nand_set_cmd()
42 fmc_pr(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in spi_nand_set_cmd()
44 reg = fmc_data_num_cnt(FEATURES_DATA_LEN); in spi_nand_set_cmd()
45 hifmc_write(host, FMC_DATA_NUM, reg); in spi_nand_set_cmd()
46 fmc_pr(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg); in spi_nand_set_cmd()
[all …]
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| /third_party/gstreamer/gstplugins_good/gst/deinterlace/tvtime/ |
| D | mmx.h | 275 #define mmx_i2r(op, imm, reg) \ argument
280 __asm__ __volatile__ ("movq %%" #reg ", %0" \
283 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
284 __asm__ __volatile__ (#op " %0, %%" #reg \
287 __asm__ __volatile__ ("movq %%" #reg ", %0" \
290 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
293 #define mmx_m2r(op, mem, reg) \ argument
298 __asm__ __volatile__ ("movq %%" #reg ", %0" \
301 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
302 __asm__ __volatile__ (#op " %0, %%" #reg \
[all …]
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