| /third_party/uboot/u-boot-2020.01/board/freescale/mx6slevk/ |
| D | mx6slevk.c | 234 static struct fsl_esdhc_cfg usdhc_cfg[3] = { variable
278 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; in board_mmc_init()
279 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
285 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
286 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
287 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
293 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
294 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
295 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
299 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/el/el6x/ |
| D | el6x.c | 261 struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
304 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
309 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
318 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
341 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
342 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
343 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
348 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; in board_mmc_init()
349 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
350 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/seco/mx6quq7/ |
| D | mx6quq7.c | 94 static struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
131 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
135 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
144 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcm058/ |
| D | pcm058.c | 149 static struct fsl_esdhc_cfg usdhc_cfg[] = { variable
216 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
222 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
232 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
255 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; in board_mmc_init()
256 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
257 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
258 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
261 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/gateworks/gw_ventana/ |
| D | common.c | 1661 static struct fsl_esdhc_cfg usdhc_cfg[2]; variable
1676 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
1677 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
1678 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
1679 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
1683 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
1684 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
1685 usdhc_cfg[0].max_bus_width = 8; in board_mmc_init()
1686 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
1691 usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/freescale/mx6sxsabresd/ |
| D | mx6sxsabresd.c | 330 static struct fsl_esdhc_cfg usdhc_cfg[3] = { variable
397 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
398 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
405 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
406 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
412 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
413 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; in board_mmc_init()
417 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
418 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/barco/platinum/ |
| D | platinum.c | 59 struct fsl_esdhc_cfg usdhc_cfg[] = { variable
107 if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { in board_mmc_getcd()
119 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
121 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/bachmann/ot1200/ |
| D | ot1200.c | 224 struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
234 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
235 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
237 usdhc_cfg[0].max_bus_width = 8; in board_mmc_init()
238 usdhc_cfg[1].max_bus_width = 4; in board_mmc_init()
257 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcl063/ |
| D | spl.c | 136 static struct fsl_esdhc_cfg usdhc_cfg[] = { variable
162 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
167 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
176 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mx6sabresd/ |
| D | mx6sabresd.c | 256 struct fsl_esdhc_cfg usdhc_cfg[3] = { variable
306 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
308 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
312 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
313 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
314 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
318 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; in board_mmc_init()
319 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
320 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/variscite/dart_6ul/ |
| D | spl.c | 139 static struct fsl_esdhc_cfg usdhc_cfg[] = { variable
165 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
170 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
179 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pfla02/ |
| D | pfla02.c | 155 static struct fsl_esdhc_cfg usdhc_cfg[] = { variable
221 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
226 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
235 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
568 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
569 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
570 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
571 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
573 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/embest/mx6boards/ |
| D | mx6boards.c | 186 struct fsl_esdhc_cfg usdhc_cfg[3] = { variable
240 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
241 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
256 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
257 usdhc_cfg[1].max_bus_width = 4; in board_mmc_init()
262 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
263 usdhc_cfg[2].max_bus_width = 4; in board_mmc_init()
275 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/imx8mq_evk/ |
| D | spl.c | 104 static struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
122 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); in board_mmc_init()
132 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); in board_mmc_init()
145 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
|
| /third_party/uboot/u-boot-2020.01/board/warp/ |
| D | warp.c | 64 static struct fsl_esdhc_cfg usdhc_cfg[1] = { variable
91 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
92 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/technexion/pico-imx7d/ |
| D | spl.c | 148 static struct fsl_esdhc_cfg usdhc_cfg[1] = { variable
161 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
162 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/advantech/imx8qm_rom7720_a1/ |
| D | spl.c | 63 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { variable
116 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
128 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
137 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/udoo/ |
| D | udoo.c | 176 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; variable
220 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
221 usdhc_cfg.max_bus_width = 4; in board_mmc_init()
223 return fsl_esdhc_initialize(bis, &usdhc_cfg); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mx6qarm2/ |
| D | mx6qarm2.c | 107 struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
136 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
137 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
156 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/technexion/pico-imx6ul/ |
| D | spl.c | 167 static struct fsl_esdhc_cfg usdhc_cfg[1] = { variable
179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
180 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/toradex/apalis_imx6/ |
| D | apalis_imx6.c | 291 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { variable
335 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; in board_mmc_init()
336 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
337 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
342 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
343 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
344 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
349 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
350 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
351 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/wandboard/ |
| D | spl.c | 432 static struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
491 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
492 usdhc_cfg[0].max_bus_width = 4; in board_mmc_init()
497 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
498 usdhc_cfg[1].max_bus_width = 4; in board_mmc_init()
508 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/liebherr/display5/ |
| D | spl.c | 281 static struct fsl_esdhc_cfg usdhc_cfg = { variable
290 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
291 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; in board_mmc_init()
293 return fsl_esdhc_initialize(bd, &usdhc_cfg); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/liebherr/mccmon6/ |
| D | spl.c | 503 static struct fsl_esdhc_cfg usdhc_cfg[2] = { variable
543 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
544 usdhc_cfg[0].max_bus_width = 8; in board_mmc_init()
548 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
549 usdhc_cfg[1].max_bus_width = 4; in board_mmc_init()
558 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
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| /third_party/uboot/u-boot-2020.01/board/congatec/cgtqmx6eval/ |
| D | cgtqmx6eval.c | 417 static struct fsl_esdhc_cfg usdhc_cfg[] = { variable
453 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
454 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
455 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
461 for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) { in board_mmc_init()
462 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
470 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; in board_mmc_init()
471 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
472 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
474 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
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