1 /*
2 * hi3516cv500.c
3 *
4 * The board init for hisilicon
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22 #include <config.h>
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/arch/platform.h>
26 #include <spi_flash.h>
27 #include <linux/mtd/mtd.h>
28 #include <nand.h>
29 #include <netdev.h>
30 #include <mmc.h>
31 #include <asm/sections.h>
32 #include <hicpu_common.h>
33 #include <asm/mach-types.h>
34 #include <cpu_func.h>
35
36 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)37 void enable_caches(void)
38 {
39 /* Enable D-cache. I-cache is already enabled in start.S */
40 dcache_enable();
41 }
42 #endif
43 static int boot_media = BOOT_MEDIA_UNKNOWN;
44
get_boot_media(void)45 int get_boot_media(void)
46 {
47 unsigned int reg_val, boot_mode, spi_device_mode;
48 int boot_media = BOOT_MEDIA_UNKNOWN;
49
50 reg_val = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
51 boot_mode = get_sys_boot_mode(reg_val);
52
53 switch (boot_mode) {
54 case BOOT_FROM_SPI:
55 spi_device_mode = get_spi_device_type(reg_val);
56 if (spi_device_mode)
57 boot_media = BOOT_MEDIA_NAND;
58 else
59 boot_media = BOOT_MEDIA_SPIFLASH;
60 break;
61 case BOOT_FROM_EMMC:
62 boot_media = BOOT_MEDIA_EMMC;
63 break;
64 default:
65 boot_media = BOOT_MEDIA_UNKNOWN;
66 break;
67 }
68 return boot_media;
69 }
70
71 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)72 void show_boot_progress(int progress)
73 {
74 printf("Boot reached stage %d\n", progress);
75 }
76 #endif
77
78 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
79
delay(unsigned long loops)80 static inline void delay(unsigned long loops)
81 {
82 __asm__ volatile("1:\n"
83 "subs %0, %1, #1\n"
84 "bne 1b" : "=r"(loops) : "0"(loops));
85 }
86
87
get_text_base(void)88 int get_text_base(void)
89 {
90 return CONFIG_SYS_TEXT_BASE;
91 }
92
boot_flag_init(void)93 static void boot_flag_init(void)
94 {
95 unsigned int reg, boot_mode, spi_device_mode;
96
97 /* get boot mode */
98 reg = __raw_readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
99 boot_mode = get_sys_boot_mode(reg);
100
101 switch (boot_mode) {
102 case BOOT_FROM_SPI:
103 spi_device_mode = get_spi_device_type(reg);
104 if (spi_device_mode)
105 boot_media = BOOT_MEDIA_NAND;
106 else
107 boot_media = BOOT_MEDIA_SPIFLASH;
108 break;
109 case BOOT_FROM_EMMC: /* emmc mode */
110 boot_media = BOOT_MEDIA_EMMC;
111 break;
112 default:
113 boot_media = BOOT_MEDIA_UNKNOWN;
114 break;
115 }
116 }
117
board_early_init_f(void)118 int board_early_init_f(void)
119 {
120 return 0;
121 }
122
123 #define UBOOT_DATA_ADDR 0x81000000UL
124 #define UBOOT_DATA_SIZE 0x80000UL
data_to_spiflash(void)125 int data_to_spiflash(void)
126 {
127 static struct spi_flash *flash = NULL;
128 void *buf = NULL;
129
130 unsigned int val;
131
132 /* 0:bus 0:cs 1000000:max_hz 0x3:spi_mode */
133 flash = spi_flash_probe(0, 0, 1000000, 0x3);
134 if (!flash) {
135 printf("Failed to initialize SPI flash\n");
136 return -1; /* -1:failed */
137 }
138
139 /* erase the address range. */
140 printf("Spi flash erase...\n");
141 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE);
142 if (val) {
143 printf("SPI flash sector erase failed\n");
144 return 1; /* 1:failed */
145 }
146
147 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
148 UBOOT_DATA_SIZE, MAP_WRBACK);
149 if (!buf) {
150 puts("Failed to map physical memory\n");
151 return 1; /* 1:failed */
152 }
153
154 /* copy the data from RAM to FLASH */
155 printf("Spi flash write...\n");
156 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf);
157 if (val) {
158 printf("SPI flash write failed, return %u\n",
159 val);
160 unmap_physmem(buf, UBOOT_DATA_SIZE);
161 return 1; /* 1:failed */
162 }
163
164 unmap_physmem(buf, UBOOT_DATA_SIZE);
165 return 0; /* 0:success */
166 }
167
data_to_nandflash(void)168 int data_to_nandflash(void)
169 {
170 struct mtd_info *nand_flash = NULL;
171 void *buf = NULL;
172 size_t length = UBOOT_DATA_SIZE;
173 unsigned int val;
174
175 nand_flash = nand_info[0];
176
177 printf("Nand flash erase...\n");
178 val = nand_erase(nand_flash, 0, UBOOT_DATA_SIZE);
179 if (val) {
180 printf("Nand flash erase failed\n");
181 return 1;
182 }
183
184 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
185 UBOOT_DATA_SIZE, MAP_WRBACK);
186 if (!buf) {
187 puts("Failed to map physical memory\n");
188 return 1;
189 }
190
191 printf("Nand flash write...\n");
192 val = nand_write(nand_flash, 0, &length, buf);
193 if (val) {
194 printf("Nand flash write failed, return %u\n",
195 val);
196 unmap_physmem(buf, UBOOT_DATA_SIZE);
197 return 1;
198 }
199
200 unmap_physmem(buf, UBOOT_DATA_SIZE);
201 return 0;
202 }
203
data_to_emmc(void)204 int data_to_emmc(void)
205 {
206 struct mmc *mmc = find_mmc_device(0);
207 void *buf = NULL;
208
209 if (!mmc)
210 return 1;
211
212 (void)mmc_init(mmc);
213
214 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
215 UBOOT_DATA_SIZE, MAP_WRBACK);
216 if (!buf) {
217 puts("Failed to map physical memory\n");
218 return 1;
219 }
220
221 printf("MMC write...\n");
222 blk_dwrite(mmc_get_blk_desc(mmc), 0, (UBOOT_DATA_SIZE >> NUM_9), buf);
223 unmap_physmem(buf, UBOOT_DATA_SIZE);
224 return 0;
225 }
save_bootdata_to_flash(void)226 int save_bootdata_to_flash(void)
227 {
228 unsigned int sd_update_flag = 0;
229 int ret = 0;
230 sd_update_flag = readl(REG_BASE_SCTL + REG_SC_GEN4);
231 if (sd_update_flag == START_MAGIC) {
232 #if defined(CONFIG_HIFMC)
233 if (boot_media == BOOT_MEDIA_SPIFLASH) {
234 ret = data_to_spiflash();
235 if (ret != 0)
236 return ret;
237 }
238 if (boot_media == BOOT_MEDIA_NAND) {
239 ret = data_to_nandflash();
240 if (ret != 0)
241 return ret;
242 }
243 #endif
244 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
245 if (boot_media == BOOT_MEDIA_EMMC) {
246 ret = data_to_emmc();
247 if (ret != 0)
248 return ret;
249 }
250 #endif
251
252 printf("update success!\n");
253 }
254
255 return 0;
256 }
257
258 int auto_update_flag = 0;
259 int bare_chip_program = 0;
260
261 #define REG_BASE_GPIO0 0x120d0000
262 #define GPIO0_0_DATA_OFST 0x4
263 #define GPIO_DIR_OFST 0x400
264
is_bare_program(void)265 int is_bare_program(void)
266 {
267 return 0;
268 }
269
is_auto_update(void)270 int is_auto_update(void)
271 {
272 #if (defined CONFIG_AUTO_SD_UPDATE) || (defined CONFIG_AUTO_USB_UPDATE)
273 /* to add some judgement if neccessary */
274 unsigned int val[NUM_3];
275
276 writel(0, REG_BASE_GPIO0 + GPIO_DIR_OFST);
277
278 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST);
279 if (val[NUM_0])
280 return 0;
281
282 udelay(10000); /* delay 10000 us */
283 val[NUM_1] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST);
284 udelay(10000); /* delay 10000 us */
285 val[NUM_2] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST);
286 udelay(10000); /* delay 10000 us */
287
288 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0)
289 return 1; /* update enable */
290 else
291 return 0;
292
293 #else
294 return 0;
295 #endif
296 }
297
misc_init_r(void)298 int misc_init_r(void)
299 {
300 #ifdef CONFIG_RANDOM_ETHADDR
301 random_init_r();
302 #endif
303 env_set("verify", "n");
304
305 #if (CONFIG_AUTO_UPDATE == 1)
306 /* auto update flag */
307 if (is_auto_update())
308 auto_update_flag = 1;
309 else
310 auto_update_flag = 0;
311
312 /* bare chip program flag */
313 if (is_bare_program())
314 bare_chip_program = 1;
315 else
316 bare_chip_program = 0;
317
318 #ifdef CFG_MMU_HANDLEOK
319 dcache_stop();
320 #endif
321
322 #ifdef CFG_MMU_HANDLEOK
323 dcache_start();
324 #endif
325
326 #endif
327
328 #if (CONFIG_AUTO_UPDATE == 1)
329 int update_flag = -1;
330 if (auto_update_flag)
331 update_flag = do_auto_update();
332 if (bare_chip_program && !auto_update_flag)
333 save_bootdata_to_flash();
334 if (update_flag == 0)
335 do_reset(NULL, 0, 0, NULL);
336 #endif
337 return 0;
338 }
339
board_init(void)340 int board_init(void)
341 {
342 DECLARE_GLOBAL_DATA_PTR;
343
344 gd->bd->bi_arch_number = MACH_TYPE_HI3516CV500;
345 gd->bd->bi_boot_params = CFG_BOOT_PARAMS;
346
347 boot_flag_init();
348
349 return 0;
350 }
351
dram_init(void)352 int dram_init(void)
353 {
354 DECLARE_GLOBAL_DATA_PTR;
355
356 gd->ram_size = PHYS_SDRAM_1_SIZE;
357 return 0;
358 }
359
reset_cpu(ulong addr)360 void reset_cpu(ulong addr)
361 {
362 /* 0x12345678:writing any value will cause a reset. */
363 writel(0x12345678, REG_BASE_SCTL + REG_SC_SYSRES);
364 while (1);
365 }
366
timer_init(void)367 int timer_init(void)
368 {
369 /*
370 * Under uboot, 0xffffffff is set to load register,]
371 * timer_clk equals BUSCLK/2/256.
372 * e.g. BUSCLK equals 50M, it will roll back after 0xffffffff/timer_clk
373 * 43980s equals 12hours
374 */
375 __raw_writel(0, CFG_TIMERBASE + REG_TIMER_CONTROL);
376 __raw_writel(~0, CFG_TIMERBASE + REG_TIMER_RELOAD);
377
378 /* 32 bit, periodic */
379 __raw_writel(CFG_TIMER_CTRL, CFG_TIMERBASE + REG_TIMER_CONTROL);
380
381 return 0;
382 }
383
board_eth_init(bd_t * bis)384 int board_eth_init(bd_t *bis)
385 {
386 int rc = 0;
387
388 #ifdef CONFIG_HISFV300_ETH
389 rc = hieth_initialize(bis);
390 #endif
391 return rc;
392 }
393
394 #ifdef CONFIG_GENERIC_MMC
board_mmc_init(bd_t * bis)395 int board_mmc_init(bd_t *bis)
396 {
397 int ret = 0;
398 int dev_num = 0;
399
400 #ifdef CONFIG_SUPPORT_EMMC_BOOT
401 ret = himci_add_port(dev_num, EMMC_REG_BASE, CONFIG_HIMCI_MAX_FREQ);
402 if (!ret) {
403 ret = himci_probe(dev_num);
404 if (ret)
405 printf("No EMMC device found !\n");
406 }
407 dev_num++;
408 #endif
409
410 #ifdef CONFIG_AUTO_SD_UPDATE
411 if (is_auto_update()) {
412 ret = himci_add_port(dev_num, SDIO0_REG_BASE, CONFIG_SDIO0_FREQ);
413 if (!ret) {
414 ret = himci_probe(dev_num);
415 if (ret)
416 printf("No SD device found !\n");
417 }
418 }
419 #endif
420
421 return ret;
422 }
423 #endif
424
start_other_cpus(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])425 int start_other_cpus(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
426 {
427 /* prepare two commands for cortex-a17 */
428 volatile int cmd_address = 0;
429 volatile int cmd = 0xe51ff004; /* 0xe51ff004:Default liteos address. */
430 unsigned int regval;
431
432 if (argc < NUM_2) {
433 cmd_usage(cmdtp);
434 return 1;
435 }
436
437 flush_dcache_all();
438 asm("str %0, [%1]"::"r"(cmd), "r"(cmd_address): "cc");
439 cmd = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
440 printf("starting cpu1 liteos address 0x%x\n", cmd);
441 asm("str %0, [%1, #4]"::"r"(cmd), "r"(cmd_address): "cc");
442 /* clear the slave cpu reset */
443 /* 0x12010000:CRG base address; 0x0078:PERI_CRG30 */
444 regval = readl(0x12010000 + 0x0078);
445 regval &= ~(NUM_1 << NUM_2);
446 /* 0x12010000:CRG base address; 0x0078:PERI_CRG30 */
447 writel(regval, (0x12010000 + 0x0078));
448 return 0;
449 }
450
451 U_BOOT_CMD(
452 go_cpu1, CONFIG_SYS_MAXARGS, 0, start_other_cpus,
453 "Perform power on and unreset CPU1_A7",
454 "go_cpu1 <address>\n"
455 );
456
457 #ifdef CONFIG_ARMV7_NONSEC
smp_set_core_boot_addr(unsigned long addr,int corenr)458 void smp_set_core_boot_addr(unsigned long addr, int corenr)
459 {
460 }
461
smp_kick_all_cpus(void)462 void smp_kick_all_cpus(void)
463 {
464 }
465
smp_waitloop(unsigned previous_address)466 void smp_waitloop(unsigned previous_address)
467 {
468 }
469 #endif
470