| /third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| D | fd3_program.c | 259 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd3_program_emit()
263 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd3_program_emit()
366 unsigned compmask = fp->inputs[j].compmask; in fd3_program_emit() local
375 if (compmask & (1 << i)) { in fd3_program_emit()
392 if (compmask & 0x1) { in fd3_program_emit()
396 if (compmask & 0x2) { in fd3_program_emit()
400 if (compmask & 0x4) { in fd3_program_emit()
405 if (compmask & 0x8) { in fd3_program_emit()
|
| D | fd3_emit.c | 389 if (!vp->inputs[i].compmask) in fd3_emit_vertex_bufs()
413 if (vp->inputs[i].compmask) { in fd3_emit_vertex_bufs()
452 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd3_emit_vertex_bufs()
461 total_in += util_bitcount(vp->inputs[i].compmask); in fd3_emit_vertex_bufs()
|
| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_shader.h | 590 uint8_t compmask; member
858 if (so->inputs[i].compmask && so->inputs[i].bary) in ir3_next_varying()
880 uint8_t compmask; member
895 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid_, uint8_t compmask, in ir3_link_add() argument
898 for (int j = 0; j < util_last_bit(compmask); j++) { in ir3_link_add()
903 l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask)); in ir3_link_add()
910 l->var[i].compmask = compmask; in ir3_link_add()
963 fs->inputs[j].compmask, fs->inputs[j].inloc); in ir3_link_shaders()
|
| D | ir3_shader.c | 80 if (v->inputs[i].compmask) { in fixup_regfootprint()
81 unsigned n = util_last_bit(v->inputs[i].compmask) - 1; in fixup_regfootprint()
719 so->inputs[i].compmask, so->inputs[i].inloc, so->inputs[i].bary); in ir3_shader_disasm()
813 unsigned compmask = in ir3_link_stream_out() local
832 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc); in ir3_link_stream_out()
837 if (compmask & ~l->var[idx].compmask) { in ir3_link_stream_out()
838 l->var[idx].compmask |= compmask; in ir3_link_stream_out()
840 l->max_loc, l->var[idx].loc + util_last_bit(l->var[idx].compmask)); in ir3_link_stream_out()
|
| D | ir3_compiler_nir.c | 64 create_input(struct ir3_context *ctx, unsigned compmask) in create_input() argument
70 __ssa_dst(in)->wrmask = compmask; in create_input()
1455 unsigned compmask, struct ir3_instruction *instr) in add_sysval_input_compmask() argument
1466 so->inputs[n].compmask = compmask; in add_sysval_input_compmask()
1469 so->sysval_in += util_last_bit(compmask); in add_sysval_input_compmask()
1474 unsigned compmask) in create_sysval_input() argument
1476 assert(compmask); in create_sysval_input()
1477 struct ir3_instruction *sysval = create_input(ctx, compmask); in create_sysval_input()
1478 add_sysval_input_compmask(ctx, slot, compmask, sysval); in create_sysval_input()
3331 unsigned compmask; in setup_input() local
[all …]
|
| D | ir3_parser.y | 230 static void add_sysval(unsigned reg, unsigned compmask, gl_system_value sysval) in add_sysval() argument
236 variant->inputs[n].compmask = compmask; in add_sysval()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | fd4_program.c | 312 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd4_program_emit()
316 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd4_program_emit()
484 unsigned compmask = s[FS].v->inputs[j].compmask; in fd4_program_emit() local
493 if (compmask & (1 << i)) { in fd4_program_emit()
511 if (compmask & 0x1) { in fd4_program_emit()
515 if (compmask & 0x2) { in fd4_program_emit()
519 if (compmask & 0x4) { in fd4_program_emit()
524 if (compmask & 0x8) { in fd4_program_emit()
|
| D | fd4_emit.c | 387 if (!vp->inputs[i].compmask) in fd4_emit_vertex_bufs()
411 if (vp->inputs[i].compmask) { in fd4_emit_vertex_bufs()
449 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd4_emit_vertex_bufs()
458 total_in += util_bitcount(vp->inputs[i].compmask); in fd4_emit_vertex_bufs()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_program.c | 449 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd5_program_emit()
453 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd5_program_emit()
627 unsigned compmask = s[FS].v->inputs[j].compmask; in fd5_program_emit() local
636 if (compmask & (1 << i)) { in fd5_program_emit()
654 if (compmask & 0x1) { in fd5_program_emit()
658 if (compmask & 0x2) { in fd5_program_emit()
662 if (compmask & 0x4) { in fd5_program_emit()
667 if (compmask & 0x8) { in fd5_program_emit()
|
| D | fd5_emit.c | 481 if (vp->inputs[i].compmask) { in fd5_emit_vertex_bufs()
520 A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd5_emit_vertex_bufs()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_program.c | 617 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in setup_stateobj()
621 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in setup_stateobj()
1046 assert(vs->inputs[i].compmask); in setup_stateobj()
1048 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) | in setup_stateobj()
1128 unsigned compmask = fs->inputs[j].compmask; in emit_interp_state() local
1136 if (compmask & (1 << i)) { in emit_interp_state()
1152 if (compmask & 0x1) { in emit_interp_state()
1156 if (compmask & 0x2) { in emit_interp_state()
1160 if (compmask & 0x4) { in emit_interp_state()
1165 if (compmask & 0x8) { in emit_interp_state()
|
| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | tu_pipeline.c | 1068 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask); in tu6_emit_vpc()
1272 const uint32_t compmask = fs->inputs[index].compmask; in tu6_vpc_varying_mode() local
1281 if (compmask & 0x1) { in tu6_vpc_varying_mode()
1285 if (compmask & 0x2) { in tu6_vpc_varying_mode()
1289 if (compmask & 0x4) { in tu6_vpc_varying_mode()
1293 if (compmask & 0x8) { in tu6_vpc_varying_mode()
1299 if (compmask & (1 << i)) { in tu6_vpc_varying_mode()
1808 .writemask = vs->inputs[input_idx].compmask, in tu6_emit_vertex_input()
|