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Searched refs:qpu (Results 1 – 25 of 25) sorted by relevance

/third_party/mesa3d/src/broadcom/compiler/
Dvir_to_qpu.c137 if (qinst->qpu.type != V3D_QPU_INSTR_TYPE_ALU || in is_no_op_mov()
138 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV || in is_no_op_mov()
139 qinst->qpu.alu.add.op != V3D_QPU_A_NOP || in is_no_op_mov()
140 memcmp(&qinst->qpu.sig, &no_sig, sizeof(no_sig)) != 0) { in is_no_op_mov()
145 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr; in is_no_op_mov()
146 if (qinst->qpu.alu.mul.magic_write) { in is_no_op_mov()
150 if (qinst->qpu.alu.mul.a != in is_no_op_mov()
157 switch (qinst->qpu.alu.mul.a) { in is_no_op_mov()
159 raddr = qinst->qpu.raddr_a; in is_no_op_mov()
162 raddr = qinst->qpu.raddr_b; in is_no_op_mov()
[all …]
Dvir_opt_redundant_flags.c45 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU); in vir_dce_pf()
47 inst->qpu.flags.apf = V3D_QPU_PF_NONE; in vir_dce_pf()
48 inst->qpu.flags.mpf = V3D_QPU_PF_NONE; in vir_dce_pf()
80 if (a->qpu.flags.apf != b->qpu.flags.apf || in vir_instr_flags_op_equal()
81 a->qpu.flags.mpf != b->qpu.flags.mpf || in vir_instr_flags_op_equal()
82 a->qpu.alu.add.op != b->qpu.alu.add.op || in vir_instr_flags_op_equal()
83 a->qpu.alu.mul.op != b->qpu.alu.mul.op || in vir_instr_flags_op_equal()
84 a->qpu.alu.add.a_unpack != b->qpu.alu.add.a_unpack || in vir_instr_flags_op_equal()
85 a->qpu.alu.add.b_unpack != b->qpu.alu.add.b_unpack || in vir_instr_flags_op_equal()
86 a->qpu.alu.add.output_pack != b->qpu.alu.add.output_pack || in vir_instr_flags_op_equal()
[all …]
Dvir_opt_dead_code.c50 assert(!v3d_qpu_writes_flags(&inst->qpu)); in dce()
69 if (c->devinfo->ver >= 41 && v3d_qpu_uses_sfu(&inst->qpu)) in can_write_to_null()
85 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU); in vir_dce_flags()
87 inst->qpu.flags.apf = V3D_QPU_PF_NONE; in vir_dce_flags()
88 inst->qpu.flags.mpf = V3D_QPU_PF_NONE; in vir_dce_flags()
89 inst->qpu.flags.auf = V3D_QPU_UF_NONE; in vir_dce_flags()
90 inst->qpu.flags.muf = V3D_QPU_UF_NONE; in vir_dce_flags()
98 if (!inst->qpu.sig.ldunifa && !inst->qpu.sig.ldunifarf) in check_last_ldunifa()
114 if (scan_inst->qpu.sig.ldunifa || scan_inst->qpu.sig.ldunifarf) in check_last_ldunifa()
127 if (!inst->qpu.sig.ldunifa && !inst->qpu.sig.ldunifarf) in check_first_ldunifa()
[all …]
Dvir_opt_copy_propagate.c43 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU || in is_copy_mov()
44 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV && in is_copy_mov()
45 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) { in is_copy_mov()
55 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE || in is_copy_mov()
56 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) { in is_copy_mov()
60 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE || in is_copy_mov()
61 inst->qpu.flags.mc != V3D_QPU_COND_NONE) { in is_copy_mov()
107 return inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
109 return inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
112 return inst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
[all …]
Dvir_opt_constant_alu.c67 switch (inst->qpu.alu.add.op) { in opt_constant_add()
74 assert(inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE); in opt_constant_add()
105 if(inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in try_opt_constant_alu()
111 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE || in try_opt_constant_alu()
112 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) { in try_opt_constant_alu()
116 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE || in try_opt_constant_alu()
117 inst->qpu.flags.mc != V3D_QPU_COND_NONE) { in try_opt_constant_alu()
126 inst->qpu.raddr_b, in try_opt_constant_alu()
136 if ((def->qpu.sig.ldunif || def->qpu.sig.ldunifrf) && in try_opt_constant_alu()
Dvir.c33 switch (inst->qpu.type) { in vir_get_nsrc()
37 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP) in vir_get_nsrc()
38 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op); in vir_get_nsrc()
40 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op); in vir_get_nsrc()
53 switch (inst->qpu.type) { in vir_has_side_effects()
57 switch (inst->qpu.alu.add.op) { in vir_has_side_effects()
71 switch (inst->qpu.alu.mul.op) { in vir_has_side_effects()
79 if (inst->qpu.sig.ldtmu || in vir_has_side_effects()
80 inst->qpu.sig.ldvary || in vir_has_side_effects()
81 inst->qpu.sig.ldtlbu || in vir_has_side_effects()
[all …]
Dqpu_schedule.c158 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n); in process_mux_deps()
161 if (!n->inst->qpu.sig.small_imm) { in process_mux_deps()
163 state->last_rf[n->inst->qpu.raddr_b], n); in process_mux_deps()
282 struct v3d_qpu_instr *inst = &qinst->qpu; in calculate_deps()
526 const struct v3d_qpu_instr *inst = &qinst->qpu; in reads_too_soon_after_write()
566 const struct v3d_qpu_instr *inst = &qinst->qpu; in writes_too_soon_after_write()
1030 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()
1040 const struct v3d_qpu_instr *inst = &n->inst->qpu; in choose_instruction_to_schedule()
1145 if ((prev_inst->inst->qpu.sig.ldunifa || in choose_instruction_to_schedule()
1146 prev_inst->inst->qpu.sig.ldunifarf) && in choose_instruction_to_schedule()
[all …]
Dvir_dump.c173 inst->qpu.raddr_b, in vir_print_reg()
177 int8_t *p = (int8_t *)&inst->qpu.raddr_b; in vir_print_reg()
218 struct v3d_qpu_sig *sig = &inst->qpu.sig; in vir_dump_sig()
224 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
230 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
234 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
238 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
244 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
250 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig()
259 struct v3d_qpu_instr *instr = &inst->qpu; in vir_dump_alu()
[all …]
Dvir_live_variables.c94 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in vir_setup_def()
114 if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE && in vir_setup_def()
115 inst->qpu.flags.mc == V3D_QPU_COND_NONE) && in vir_setup_def()
116 inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE && in vir_setup_def()
117 inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) { in vir_setup_def()
134 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE || in vir_setup_def()
135 inst->qpu.flags.mc != V3D_QPU_COND_NONE) { in vir_setup_def()
172 if (inst->qpu.flags.apf != V3D_QPU_PF_NONE || in vir_setup_def_use()
173 inst->qpu.flags.mpf != V3D_QPU_PF_NONE) { in vir_setup_def_use()
177 if (inst->qpu.flags.auf != V3D_QPU_UF_NONE || in vir_setup_def_use()
[all …]
Dvir_opt_small_immediates.c41 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in vir_opt_small_immediates()
63 if (!src_def || !src_def->qpu.sig.ldunif) in vir_opt_small_immediates()
81 struct v3d_qpu_sig new_sig = inst->qpu.sig; in vir_opt_small_immediates()
92 inst->qpu.sig.small_imm = true; in vir_opt_small_immediates()
93 inst->qpu.raddr_b = packed; in vir_opt_small_immediates()
Dvir_register_allocate.c42 inst->qpu.sig.wrtmuc; in qinst_writes_tmu()
49 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && in is_end_of_tmu_sequence()
50 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) { in is_end_of_tmu_sequence()
54 if (!inst->qpu.sig.ldtmu) in is_end_of_tmu_sequence()
59 if (scan_inst->qpu.sig.ldtmu) in is_end_of_tmu_sequence()
62 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && in is_end_of_tmu_sequence()
63 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) { in is_end_of_tmu_sequence()
79 return def && def->qpu.sig.ldunif; in vir_is_mov_uniform()
142 if (inst->qpu.sig.ldvary) { in v3d_choose_spill_node()
150 if (v3d_qpu_writes_vpm(&inst->qpu) || in v3d_choose_spill_node()
[all …]
Dqpu_validate.c65 v3d_qpu_dump(c->devinfo, &inst->qpu); in fail_instr()
113 const struct v3d_qpu_instr *inst = &qinst->qpu; in qpu_validate_inst()
299 state->last = &qinst->qpu; in qpu_validate_block()
Dv3d_compiler.h160 struct v3d_qpu_instr qpu; member
1378 ldtmu->qpu.sig.ldtmu = true; in vir_LDTMU()
1382 vir_NOP(c)->qpu.sig.ldtmu = true; in vir_LDTMU()
1402 ldtlb->qpu.sig.ldtlbu = true; in vir_TLBU_COLOR_READ()
1414 ldtlb->qpu.sig.ldtlb = true; in vir_TLB_COLOR_READ()
Dnir_to_vir.c164 c->last_thrsw->qpu.sig.thrsw = true; in vir_emit_thrsw()
728 is_ldunif_signal(&c->defs[result.index]->qpu.sig) && in ntq_store_dest()
761 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig))) { in ntq_store_dest()
998 ldvary->qpu.sig.ldvary = true; in emit_fragment_varying()
1001 vir_NOP(c)->qpu.sig.ldvary = true; in emit_fragment_varying()
2703 ldunifa->qpu.sig.ldunifa = true; in emit_ldunifa()
3378 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_uniform_if()
3419 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_uniform_if()
3688 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_nonuniform_loop()
3908 if (inst->qpu.sig.thrsw) in vir_remove_thrsw()
Dv3d40_tex.c58 inst->qpu.sig.wrtmuc = true; in vir_WRTMUC()
/third_party/mesa3d/src/broadcom/
Dmeson.build30 subdir('qpu') subdir
/third_party/mesa3d/docs/relnotes/
D18.0.0.rst217 - mesa-17.3.0/src/broadcom/qpu/qpu_pack.c:171]: (error) Invalid
D21.3.0.rst217 - broadcom/qpu: update/remove comments
218 - broadcom/qpu: add new lookup opcode description helper
219 - broadcom/qpu: use and expand version info at opcode description
2306 - broadcom/qpu: remove duplicated opcode variable
4280 - broadcom/compiler: Fix qpu.flags.muf typo.
D19.1.0.rst1412 - v3d: Add support for vir-to-qpu of ldunif instructions to a temp.
D20.1.0.rst234 - src/broadcom/qpu/qpu_pack.c:962:25: error: implicit declaration of
D20.2.0.rst3647 - broadcom/qpu: set VC5_QPU_RADDR_A out of the switch at _pack_branch
D21.2.0.rst3180 - broadcom/qpu: rename from VC5 to V3D
D21.1.0.rst1802 - v3d/qpu: Avoid leaking memory in the QPU disasm test.
/third_party/mesa3d/docs/
Denvvars.rst588 ``qpu``
/third_party/mesa3d/ohos/
Ddependency_inputs.gni671 ../src/broadcom/qpu/meson.build
672 ../src/broadcom/qpu/qpu_disasm.c
673 ../src/broadcom/qpu/qpu_disasm.h
674 ../src/broadcom/qpu/qpu_instr.c
675 ../src/broadcom/qpu/qpu_instr.h
676 ../src/broadcom/qpu/qpu_pack.c
677 ../src/broadcom/qpu/qpu_validate.c