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Searched refs:regid (Results 1 – 25 of 37) sorted by relevance

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/third_party/mesa3d/src/freedreno/ir3/
Dir3_shader.c77 if (v->inputs[i].regid >= regid(48, 0)) in fixup_regfootprint()
82 int32_t regid = v->inputs[i].regid + n; in fixup_regfootprint() local
85 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); in fixup_regfootprint()
87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint()
90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint()
97 if (!VALIDREG(v->outputs[i].regid)) in fixup_regfootprint()
99 int32_t regid = v->outputs[i].regid + 3; in fixup_regfootprint() local
102 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); in fixup_regfootprint()
104 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint()
107 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint()
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Dir3_shader.h565 uint8_t regid; member
589 uint8_t regid; member
879 uint8_t regid; member
905 if (regid_ != regid(63, 0)) { in ir3_link_add()
909 l->var[i].regid = regid_; in ir3_link_add()
928 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0); in ir3_link_shaders()
962 ir3_link_add(l, k >= 0 ? vs->outputs[k].regid : default_regid, in ir3_link_shaders()
973 uint32_t regid = so->outputs[j].regid; in ir3_find_output_regid() local
975 regid |= HALF_REG_ID; in ir3_find_output_regid()
976 return regid; in ir3_find_output_regid()
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Dir3_legalize.c215 if (last_rel && (reg->num == regid(REG_A0, 0))) { in legalize_block()
319 ir3_dst_create(baryf, regid(63, 0), 0); in legalize_block()
321 ir3_src_create(baryf, regid(0, 0), 0); in legalize_block()
349 ir3_dst_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI; in legalize_block()
351 ir3_src_create(baryf, regid(0, 0), 0); in legalize_block()
687 ir3_src_create(br1, regid(REG_P0, 0), 0)->def = in block_sched()
694 ir3_src_create(br2, regid(REG_P0, 0), 0)->def = in block_sched()
Dir3_compiler_nir.c107 unsigned r = regid(n + dp / 4, dp % 4); in create_driver_param()
782 unsigned ubo = regid(const_state->offsets.ubo, 0); in emit_intrinsic_load_ubo()
2039 cond->dsts[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2052 kill->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2072 cond->dsts[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2092 dst[0]->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2110 dst[0]->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
2134 ballot->srcs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
3204 cond->dsts[0]->num = regid(REG_P0, 0); in emit_stream_out()
3228 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i)); in emit_stream_out()
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Dinstr-a3xx.h417 regid(int num, int comp) in regid() function
422 #define INVALID_REG regid(63, 0)
Dir3_cp_postsched.c67 (instr->dsts[0]->num == regid(REG_A0, 0))) in has_conflicting_write()
Dir3_context.c447 instr->dsts[0]->num = regid(REG_A0, 0); in create_addr0()
458 instr->dsts[0]->num = regid(REG_A0, 1); in create_addr1()
520 cond->dsts[0]->num = regid(REG_P0, 0); in ir3_get_predicate()
Dir3.h832 if (dst->num == regid(REG_P0, 0)) in is_same_type_mov()
1094 if ((reg_num(dst) == REG_A0) || (dst->num == regid(REG_P0, 0))) in is_dest_gpr()
1113 return dst->num == regid(REG_A0, 0); in writes_addr0()
1124 return dst->num == regid(REG_A0, 1); in writes_addr1()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_const.c38 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_user() argument
41 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_user()
52 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS, in fd6_emit_const_user()
60 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS, in fd6_emit_const_user()
69 const struct ir3_shader_variant *v, uint32_t regid, in fd6_emit_const_bo() argument
72 uint32_t dst_off = regid / 4; in fd6_emit_const_bo()
77 emit_const_asserts(ring, v, regid, sizedwords); in fd6_emit_const_bo()
116 const unsigned regid = const_state->offsets.primitive_param * 4 + 4; in emit_tess_bos() local
120 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) | in emit_tess_bos()
133 const unsigned regid = const_state->offsets.primitive_param; in emit_stage_tess_consts() local
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Dfd6_compute.c91 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in cs_program_emit()
92 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in cs_program_emit()
94 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in cs_program_emit()
100 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in cs_program_emit()
101 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in cs_program_emit()
103 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in cs_program_emit()
Dfd6_program.c213 if (l->var[idx].regid == v->outputs[k].regid) in setup_stream_out()
348 return regid(63, 0); in next_regid()
401 vs_primitive_regid = regid(63, 0); in setup_stateobj()
420 tess_coord_x_regid = regid(63, 0); in setup_stateobj()
421 tess_coord_y_regid = regid(63, 0); in setup_stateobj()
422 hs_rel_patch_regid = regid(63, 0); in setup_stateobj()
423 ds_rel_patch_regid = regid(63, 0); in setup_stateobj()
424 ds_primitive_regid = regid(63, 0); in setup_stateobj()
425 hs_invocation_regid = regid(63, 0); in setup_stateobj()
438 gs_header_regid = regid(63, 0); in setup_stateobj()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_emit.c56 const struct ir3_shader_variant *v, uint32_t regid, in fd4_emit_const_user() argument
59 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_user()
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd4_emit_const_user()
74 const struct ir3_shader_variant *v, uint32_t regid, in fd4_emit_const_bo() argument
77 uint32_t dst_off = regid / 4; in fd4_emit_const_bo()
82 emit_const_asserts(ring, v, regid, sizedwords); in fd4_emit_const_bo()
94 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd4_emit_const_ptrs() argument
100 debug_assert((regid % 4) == 0); in fd4_emit_const_ptrs()
103 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd4_emit_const_ptrs()
381 unsigned vertex_regid = regid(63, 0); in fd4_emit_vertex_bufs()
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Dfd4_program.c177 if (pos_regid == regid(63, 0)) { in fd4_program_emit()
182 pos_regid = regid(0, 0); in fd4_program_emit()
204 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2); in fd4_program_emit()
311 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd4_program_emit()
315 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd4_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_emit.c61 const struct ir3_shader_variant *v, uint32_t regid, in fd3_emit_const_user() argument
64 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_user()
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) | in fd3_emit_const_user()
79 const struct ir3_shader_variant *v, uint32_t regid, in fd3_emit_const_bo() argument
82 uint32_t dst_off = regid / 2; in fd3_emit_const_bo()
91 emit_const_asserts(ring, v, regid, sizedwords); in fd3_emit_const_bo()
103 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd3_emit_const_ptrs() argument
109 debug_assert((regid % 4) == 0); in fd3_emit_const_ptrs()
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) | in fd3_emit_const_ptrs()
383 unsigned vertex_regid = regid(63, 0); in fd3_emit_vertex_bufs()
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Dfd3_program.c174 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2); in fd3_program_emit()
258 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd3_program_emit()
262 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd3_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_const.h43 const struct ir3_shader_variant *v, uint32_t regid,
47 const struct ir3_shader_variant *v, uint32_t regid,
52 uint32_t regid, uint32_t offset, uint32_t size, in emit_const_prsc() argument
56 emit_const_bo(ring, v, regid, offset, size, rsc->bo); in emit_const_prsc()
66 const struct ir3_shader_variant *v, uint32_t regid, in emit_const_asserts() argument
69 assert((regid % 4) == 0); in emit_const_asserts()
71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts()
474 regid(63, 0); in ir3_emit_vs_driver_params()
/third_party/mesa3d/src/freedreno/computerator/
Da4xx.c138 A4XX_HLSQ_CL_CONTROL_0_UNK12CONSTID(regid(63, 0)) | in cs_program_emit()
140 OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(regid(63, 0)) | in cs_program_emit()
141 A4XX_HLSQ_CL_CONTROL_1_UNK12CONSTID(regid(63, 0))); in cs_program_emit()
144 OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(regid(63, 0)) | in cs_program_emit()
148 OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(regid(63, 0))); in cs_program_emit()
Da6xx.c168 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in cs_program_emit()
169 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in cs_program_emit()
171 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in cs_program_emit()
211 emit_const(struct fd_ringbuffer *ring, uint32_t regid, uint32_t sizedwords, in emit_const() argument
216 debug_assert((regid % 4) == 0); in emit_const()
221 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) | in emit_const()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_emit.c59 const struct ir3_shader_variant *v, uint32_t regid, in fd5_emit_const_user() argument
62 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_user()
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd5_emit_const_user()
78 const struct ir3_shader_variant *v, uint32_t regid, in fd5_emit_const_bo() argument
81 uint32_t dst_off = regid / 4; in fd5_emit_const_bo()
86 emit_const_asserts(ring, v, regid, sizedwords); in fd5_emit_const_bo()
98 uint32_t regid, uint32_t num, struct fd_bo **bos, in fd5_emit_const_ptrs() argument
104 debug_assert((regid % 4) == 0); in fd5_emit_const_ptrs()
107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | in fd5_emit_const_ptrs()
521 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid)); in fd5_emit_vertex_bufs()
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Dfd5_compute.c98 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | in cs_program_emit()
99 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | in cs_program_emit()
Dfd5_program.c108 if (l->var[idx].regid == v->outputs[k].regid) in emit_stream_out()
234 return regid(63, 0); in next_regid()
448 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd5_program_emit()
452 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd5_program_emit()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c652 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in tu6_emit_cs_config()
653 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in tu6_emit_cs_config()
655 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in tu6_emit_cs_config()
662 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) | in tu6_emit_cs_config()
663 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) | in tu6_emit_cs_config()
665 tu_cs_emit(cs, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) | in tu6_emit_cs_config()
684 regid(63, 0); in tu6_emit_vs_system_values()
687 regid(63, 0); in tu6_emit_vs_system_values()
690 regid(63, 0); in tu6_emit_vs_system_values()
693 regid(63, 0); in tu6_emit_vs_system_values()
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/third_party/mesa3d/src/freedreno/decode/
Dpgmdump2.c277 uint32_t regid; member
287 R(c, regid, 'c'); in decode_shader_constant_block()
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_valtable.cpp367 value* sb_value_pool::create(value_kind k, sel_chan regid, in create() argument
370 value *v = new (np) value(size(), k, regid, ver); in create()
Dsb_shader.cpp246 value* shader::create_value(value_kind k, sel_chan regid, unsigned ver) { in create_value() argument
247 value *v = val_pool.create(k, regid, ver); in create_value()

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