Searched +full:0 +full:x10003000 (Results 1 – 25 of 28) sorted by relevance
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/ |
D | mediatek,pericfg.yaml | 56 reg = <0x10003000 0x1000>; 64 reg = <0x10003000 0x1000>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
D | fsl,imxgpt.yaml | 67 reg = <0x10003000 0x1000>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/ |
D | ingenic,rtc.yaml | 49 minimum: 0 57 minimum: 0 78 reg = <0x10003000 0x40>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | hip01.dtsi | 19 #address-cells = <0>; 21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; 26 #clock-cells = <0>; 36 ranges = <0 0x10000000 0x20000000>; 46 reg = <0x10001000 0x1000>; 50 interrupts = <0 32 4>; 56 reg = <0x10002000 0x1000>; 60 interrupts = <0 33 4>; 66 reg = <0x10003000 0x1000>; 70 interrupts = <0 34 4>; [all …]
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D | mt8135.dtsi | 42 #size-cells = <0>; 45 cpu0: cpu@0 { 48 reg = <0x000>; 54 reg = <0x001>; 60 reg = <0x100>; 66 reg = <0x101>; 77 reg = <0 0x80002000 0 0x1000>; 90 #clock-cells = <0>; 96 #clock-cells = <0>; 101 #clock-cells = <0>; [all …]
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D | versatile-ab.dts | 24 reg = <0x0 0x08000000>; 28 #clock-cells = <0>; 36 #size-cells = <0>; 40 #size-cells = <0>; 42 port@0 { 43 reg = <0>; 72 reg = <0x10000000 0x200>; 76 offset = <0x08>; 77 mask = <0x01>; 78 label = "versatile:0"; [all …]
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D | imx27.dtsi | 47 reg = <0x10040000 0x1000>; 53 #clock-cells = <0>; 59 #size-cells = <0>; 62 cpu: cpu@0 { 64 reg = <0>; 88 reg = <0x10000000 0x20000>; 93 reg = <0x10001000 0x1000>; 104 reg = <0x10002000 0x1000>; 111 reg = <0x10003000 0x1000>; 120 reg = <0x10004000 0x1000>; [all …]
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D | mt2701.dtsi | 25 #size-cells = <0>; 28 cpu@0 { 31 reg = <0x0>; 36 reg = <0x1>; 41 reg = <0x2>; 46 reg = <0x3>; 57 reg = <0 0x80002000 0 0x1000>; 64 #clock-cells = <0>; 70 #clock-cells = <0>; 73 clk26m: oscillator@0 { [all …]
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D | mt7623.dtsi | 73 #size-cells = <0>; 76 cpu0: cpu@0 { 79 reg = <0x0>; 91 reg = <0x1>; 103 reg = <0x2>; 115 reg = <0x3>; 137 #clock-cells = <0>; 142 #clock-cells = <0>; 147 clk26m: oscillator-0 { 149 #clock-cells = <0>; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
D | interrupts.txt | 17 interrupts = <5 0>, <6 0>; 31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; 55 reg = <0x10140000 0x1000>; 62 reg = <0x10003000 0x1000>; 72 - bits[3:0] trigger type and level flags 83 reg = <0x41>; 99 reg = <0x2b>; 102 interrupts = <3 0x8>; 105 #size-cells = <0>; 107 threshold = <0x40>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/ |
D | sc9836.dtsi | 17 #size-cells = <0>; 19 cpu0: cpu@0 { 22 reg = <0x0 0x0>; 29 reg = <0x0 0x1>; 36 reg = <0x0 0x2>; 43 reg = <0x0 0x3>; 50 reg = <0 0x10003000 0 0x1000>; 64 reg = <0 0x10001000 0 0x1000>; 78 #size-cells = <0>; 80 port@0 { [all …]
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D | sc9863a.dtsi | 15 #size-cells = <0>; 46 CPU0: cpu@0 { 49 reg = <0x0 0x0>; 57 reg = <0x0 0x100>; 65 reg = <0x0 0x200>; 73 reg = <0x0 0x300>; 81 reg = <0x0 0x400>; 89 reg = <0x0 0x500>; 97 reg = <0x0 0x600>; 105 reg = <0x0 0x700>; [all …]
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D | sc9860.dtsi | 17 #size-cells = <0>; 54 reg = <0x0 0x530000>; 62 reg = <0x0 0x530001>; 70 reg = <0x0 0x530002>; 78 reg = <0x0 0x530003>; 86 reg = <0x0 0x530100>; 94 reg = <0x0 0x530101>; 102 reg = <0x0 0x530102>; 110 reg = <0x0 0x530103>; 125 arm,psci-suspend-param = <0x00010002>; [all …]
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/kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/ |
D | rt3883.h | 13 #define RT3883_SDRAM_BASE 0x00000000 14 #define RT3883_SYSC_BASE 0x10000000 15 #define RT3883_TIMER_BASE 0x10000100 16 #define RT3883_INTC_BASE 0x10000200 17 #define RT3883_MEMC_BASE 0x10000300 18 #define RT3883_UART0_BASE 0x10000500 19 #define RT3883_PIO_BASE 0x10000600 20 #define RT3883_FSCC_BASE 0x10000700 21 #define RT3883_NANDC_BASE 0x10000810 22 #define RT3883_I2C_BASE 0x10000900 [all …]
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/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/ |
D | x1000.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 18 reg = <0>; 26 #address-cells = <0>; 34 reg = <0x10001000 0x50>; 45 #clock-cells = <0>; 50 #clock-cells = <0>; 56 reg = <0x10000000 0x100>; 66 reg = <0x10002000 0x1000>; [all …]
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D | x1830.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu2.0-mxu2.0"; 18 reg = <0>; 26 #address-cells = <0>; 34 reg = <0x10001000 0x50>; 45 #clock-cells = <0>; 50 #clock-cells = <0>; 56 reg = <0x10000000 0x100>; 66 reg = <0x10002000 0x1000>; [all …]
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D | jz4740.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-mxu1.0"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x14>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 65 reg = <0x10002000 0x1000>; [all …]
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D | jz4725b.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-mxu1.0"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x14>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 65 reg = <0x10002000 0x1000>; [all …]
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D | jz4770.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x40>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 58 ranges = <0x0 0x10000000 0x100>; [all …]
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D | jz4780.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 18 reg = <0>; 26 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 35 #address-cells = <0>; 43 reg = <0x10001000 0x50>; 54 #clock-cells = <0>; 59 #clock-cells = <0>; 65 reg = <0x10000000 0x100>; [all …]
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/kernel/linux/linux-5.10/drivers/clk/imx/ |
D | clk-imx27.c | 16 #define MX27_CCM_BASE_ADDR 0x10027000 17 #define MX27_GPT1_BASE_ADDR 0x10003000 23 #define CCM_CSCR (ccm + 0x00) 24 #define CCM_MPCTL0 (ccm + 0x04) 25 #define CCM_MPCTL1 (ccm + 0x08) 26 #define CCM_SPCTL0 (ccm + 0x0c) 27 #define CCM_SPCTL1 (ccm + 0x10) 28 #define CCM_PCDR0 (ccm + 0x18) 29 #define CCM_PCDR1 (ccm + 0x1c) 30 #define CCM_PCCR0 (ccm + 0x20) [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port: 30 - cell 1 denotes the upper 32 address bits and should be 0 45 - 0x81000000: I/O memory region 46 - 0x82000000: non-prefetchable memory region 47 - 0xc2000000: prefetchable memory region 73 - pinctrl-0: phandle for the default/active state of pin configurations. 104 - If lanes 0 to 3 are used: 150 - Root port 0 uses 4 lanes, root port 1 is unused. 158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. 171 reg = <0x80003000 0x00000800 /* PADS registers */ [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
D | mt8183.dtsi | 38 #size-cells = <0>; 72 cpu0: cpu@0 { 75 reg = <0x000>; 86 reg = <0x001>; 97 reg = <0x002>; 108 reg = <0x003>; 119 reg = <0x100>; 130 reg = <0x101>; 141 reg = <0x102>; 152 reg = <0x103>; [all …]
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D | mt2712e.dtsi | 66 #size-cells = <0>; 85 cpu0: cpu@0 { 88 reg = <0x000>; 100 reg = <0x001>; 113 reg = <0x200>; 126 CPU_SLEEP_0: cpu-sleep-0 { 132 arm,psci-suspend-param = <0x0010000>; 135 CLUSTER_SLEEP_0: cluster-sleep-0 { 141 arm,psci-suspend-param = <0x1010000>; 154 #clock-cells = <0>; [all …]
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/kernel/linux/linux-5.10/arch/mips/include/asm/mach-au1x00/ |
D | au1000.h | 105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ 110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ 111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ 112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ 113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ 114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ 115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ 116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ [all …]
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