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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dinterconnect.txt1 Interconnect Provider Device Tree Bindings
4 The purpose of this document is to define a common set of generic interconnect
8 = interconnect providers =
10 The interconnect provider binding is intended to represent the interconnect
11 controllers in the system. Each provider registers a set of interconnect
12 nodes, which expose the interconnect related capabilities of the interconnect
14 etc. The consumer drivers set constraints on interconnect path (or endpoints)
15 depending on the use case. Interconnect providers can also be interconnect
16 consumers, such as in the case where two network-on-chip fabrics interface
20 - compatible : contains the interconnect provider compatible string
[all …]
Dqcom,msm8916.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8916.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8916 Network-On-Chip interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
13 The Qualcomm MSM8916 interconnect providers support adjusting the
19 - qcom,msm8916-bimc
20 - qcom,msm8916-pcnoc
21 - qcom,msm8916-snoc
[all …]
Dqcom,qcs404.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCS404 Network-On-Chip interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
13 The Qualcomm QCS404 interconnect providers support adjusting the
22 - qcom,qcs404-bimc
23 - qcom,qcs404-pcnoc
24 - qcom,qcs404-snoc
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Dqcom,msm8974.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8974.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8974 Network-On-Chip Interconnect
10 - Brian Masney <masneyb@onstation.org>
13 The Qualcomm MSM8974 interconnect providers support setting system
14 bandwidth requirements between various network-on-chip fabrics.
22 - qcom,msm8974-bimc
23 - qcom,msm8974-cnoc
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Dqcom,osm-l3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
10 - Sibi Sankar <sibis@codeaurora.org>
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
20 - qcom,sc7180-osm-l3
21 - qcom,sdm845-osm-l3
22 - qcom,sm8150-osm-l3
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Dqcom,rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
11 - Odelu Kukatla <okukatla@codeaurora.org>
14 RPMh interconnect providers support system bandwidth requirements through
27 - qcom,sc7180-aggre1-noc
28 - qcom,sc7180-aggre2-noc
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Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
22 interconnect IPs into imx SOCs.
27 - items:
28 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/
Dti-sysc.txt1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
8 of the interconnect.
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
15 space of the first child device IP block managed by the interconnect
20 - compatible shall be one of the following generic types:
23 "ti,sysc-omap2"
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Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddpu.txt6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
23 - interrupts: interrupt signal from MDSS.
24 - interrupt-controller: identifies the node as an interrupt controller.
25 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
[all …]
Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
9 with the chip-id.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
22 - qcom,adreno-630.2
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dqcom,ipa.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alex Elder <elder@kernel.org>
21 and has a distinct interrupt and a separately-defined address space.
23 See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt. See
28 - |
29 -------- ---------
31 | AP +<---. .----+ Modem |
32 | +--. | | .->+ |
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
Dsm8150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-aoss-qmp.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
[all …]
Dsm8250.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/
Dl4.txt1 L4 interconnect bindings
3 These bindings describe the OMAP SoCs L4 interconnect bus.
6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/sunxi/
Dallwinner,sun4i-a10-mbus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
20 the interconnects and interconnect-names properties set to the MBUS
21 controller and with "dma-mem" as the interconnect name.
24 "#interconnect-cells":
31 - allwinner,sun5i-a13-mbus
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
[all …]
Domap4.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Domap-mcpdm.txt4 - compatible: "ti,omap4-mcpdm"
5 - reg: Register location and size as an array:
7 <L3 interconnect address, size>;
8 - interrupts: Interrupt number for McPDM
9 - ti,hwmods: Name of the hwmod associated to the McPDM
10 - clocks: phandle for the pdmclk provider, likely <&twl6040>
11 - clock-names: Must be "pdmclk"
16 compatible = "ti,omap4-mcpdm";
18 <0x49032000 0x7f>; /* L3 Interconnect */
20 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dallwinner,sun8i-h3-deinterlace.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jernej Skrabec <jernej.skrabec@siol.net>
11 - Chen-Yu Tsai <wens@csie.org>
12 - Maxime Ripard <mripard@kernel.org>
14 description: |-
21 - const: allwinner,sun8i-h3-deinterlace
22 - items:
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