Searched refs:IO_DEVICE_ADDR (Results 1 – 21 of 21) sorted by relevance
33 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000)42 #define IO_CTL_REG_BASE IO_DEVICE_ADDR(0x10FF0000)45 #define GPIO11_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xb000)46 #define GPIO10_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xa000)47 #define GPIO9_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x9000)48 #define GPIO8_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x8000)49 #define GPIO7_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x7000)50 #define GPIO6_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x6000)51 #define GPIO5_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x5000)52 #define GPIO4_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x4000)[all …]
103 #define EMMC_PHY_BASE IO_DEVICE_ADDR(0x12160000)128 #define REG_CTRL_BASE IO_DEVICE_ADDR(0x100C0040)130 #define REG_CTRL_SDIO0_CLK IO_DEVICE_ADDR(0x100C0040)131 #define REG_CTRL_SDIO0_CMD IO_DEVICE_ADDR(0x100C0044)132 #define REG_CTRL_SDIO0_DATA0 IO_DEVICE_ADDR(0x100C0048)133 #define REG_CTRL_SDIO0_DATA1 IO_DEVICE_ADDR(0x100C004C)134 #define REG_CTRL_SDIO0_DATA2 IO_DEVICE_ADDR(0x100C0050)135 #define REG_CTRL_SDIO0_DATA3 IO_DEVICE_ADDR(0x100C0054)137 #define REG_CTRL_SDIO0_CD_DET IO_DEVICE_ADDR(0x100C005C)139 #define REG_CTRL_SDIO0_CD_POW IO_DEVICE_ADDR(0x120C0020)[all …]
65 #define EMMC_PHY_INIT_CTRL IO_DEVICE_ADDR(0x12160004)69 #define EMMC_PHY_IOCTL_RONSEL_1_0 IO_DEVICE_ADDR(0x12160264)72 #define EMMC_PHY_IOCTL_OD_RONSEL_2 IO_DEVICE_ADDR(0x12160268)73 #define EMMC_PHY_IOCTL_IOE IO_DEVICE_ADDR(0x1216026c)
33 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000)42 #define PERIPH_REG_BASE IO_DEVICE_ADDR(0x12000000)43 #define IO_CTL_REG_VBASE IO_DEVICE_ADDR(0x10F00000)50 #define ETH_REG_BASE IO_DEVICE_ADDR(0x10040000)52 #define DMAC_REG_BASE IO_DEVICE_ADDR(0x100b0000)53 #define IO_MUX_REG_BASE IO_DEVICE_ADDR(0x100c0000)55 #define IO_CTL_REG_BASE IO_DEVICE_ADDR(0x10FF0000)57 #define GPIO_REG_BASE IO_DEVICE_ADDR(0x120b0000)69 #define SPI0_REG_BASE IO_DEVICE_ADDR(0x12070000)70 #define SPI1_REG_BASE IO_DEVICE_ADDR(0x12071000)[all …]
27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000)32 #define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR)33 #define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset C…84 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000)89 #define TIMER7_REG_BASE IO_DEVICE_ADDR(0x12003020)90 #define TIMER6_REG_BASE IO_DEVICE_ADDR(0x12003000)91 #define TIMER5_REG_BASE IO_DEVICE_ADDR(0x12002020)92 #define TIMER4_REG_BASE IO_DEVICE_ADDR(0x12002000)93 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020)94 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000)[all …]
38 #define REG_CTRL_SD_CLK IO_DEVICE_ADDR(0x100C0040)39 #define REG_CTRL_SD_CMD IO_DEVICE_ADDR(0x100C0044)40 #define REG_CTRL_SD_DATA0 IO_DEVICE_ADDR(0x100C0048)41 #define REG_CTRL_SD_DATA1 IO_DEVICE_ADDR(0x100C004C)42 #define REG_CTRL_SD_DATA2 IO_DEVICE_ADDR(0x100C0050)43 #define REG_CTRL_SD_DATA3 IO_DEVICE_ADDR(0x100C0054)45 #define REG_CTRL_EMMC_CLK IO_DEVICE_ADDR(0x100C0014)46 #define REG_CTRL_EMMC_CMD IO_DEVICE_ADDR(0x100C0018)47 #define REG_CTRL_EMMC_DATA0 IO_DEVICE_ADDR(0x100C0020)48 #define REG_CTRL_EMMC_DATA1 IO_DEVICE_ADDR(0x100C001c)[all …]
27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000)77 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000)88 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000)89 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020)90 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000)91 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020)112 #define UART0_REG_BASE IO_DEVICE_ADDR(0x12040000)
28 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000)79 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x08000000)90 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000)91 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020)92 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000)93 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020)114 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000)
32 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000)37 #define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR)38 #define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset C…124 #define UART4_REG_BASE IO_DEVICE_ADDR(UART4_REG_PBASE)
32 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x08000000)36 #define CRG_REG_BASE IO_DEVICE_ADDR(0x12010000)38 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000)
124 #define REG_CTRL_EMMC_START IO_DEVICE_ADDR(0x10ff0000 + 0x0) /* eMMC pad ctrl reg */125 #define REG_CTRL_SD_START IO_DEVICE_ADDR(0x10ff0000 + 0x24) /* sd pad ctrl reg */126 #define REG_CTRL_SDIO_START IO_DEVICE_ADDR(0x112f0000 + 0x8) /* sdio pad ctrl reg */
82 int reg = IO_DEVICE_ADDR(ADDR); \89 …int reg = IO_DEVICE_ADDR(ADDR); …
90 val = readl(IO_DEVICE_ADDR(PWR_CTRL0_REG)); in SDIO_setup()92 writel(val, IO_DEVICE_ADDR(PWR_CTRL0_REG)); in SDIO_setup()
99 #define HDF_IO_DEVICE_ADDR IO_DEVICE_ADDR
28 #define IO_DEVICE_ADDR(paddr) (paddr) macro
44 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
39 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
42 void *base = (void *)IO_DEVICE_ADDR(DEBUG_UART_BASE); in UartPuts()
3157 #define EXTI ((EXTI_TypeDef *) IO_DEVICE_ADDR(EXTI_BASE))3199 #define RCC ((RCC_TypeDef *) IO_DEVICE_ADDR(RCC_BASE))