| /device/soc/rockchip/rk3588/kernel/arch/arm64/boot/dts/rockchip/ |
| D | rk3588s.dtsi | 6 #include "../../../../../include/dt-bindings/clock/rk3588-cru.h"
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <702000000>;
83 clock-output-names = "spll";
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <32768>;
90 clock-output-names = "xin32k";
94 compatible = "fixed-clock";
[all …]
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| D | rk3588.dtsi | 97 clock-names = "ref", "suspend", "bus";
151 clock-names = "phyclk";
152 clock-output-names = "usb480m_phy1";
153 #clock-cells = <0>;
177 clock-names = "pclk_csi2host";
191 clock-names = "pclk_csi2host";
203 clock-names = "mclk", "hclk";
206 assigned-clock-parents = <&cru PLL_AUPLL>;
217 clock-names = "mclk_tx", "hclk";
219 assigned-clock-parents = <&cru PLL_AUPLL>;
[all …]
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| D | .rk3588-bearkey-bq3588c1-linux.dtb.dts.tmp | 36 # 1 "vendor/arch/arm64/boot/dts/rockchip/../../../../../include/dt-bindings/clock/rk3588-cru.h" 1
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <702000000>;
124 clock-output-names = "spll";
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <32768>;
131 clock-output-names = "xin32k";
135 compatible = "fixed-clock";
[all …]
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| /device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/ |
| D | spinand.h | 47 static void hisnfc100_set_system_clock(int clock, int clk_en) in hisnfc100_set_system_clock() argument
52 if (!clock) in hisnfc100_set_system_clock()
53 clock = SPI_NAND_CLK_SEL_75M; in hisnfc100_set_system_clock()
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
66 static void hisnfc100_get_best_clock(unsigned int *clock) in hisnfc100_get_best_clock() argument
81 if (*clock < sysclk[ix]) in hisnfc100_get_best_clock()
85 *clock = clk_reg; in hisnfc100_get_best_clock()
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| D | spinor.h | 50 static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) in hisfc350_set_system_clock() argument
56 if (clock) { in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
72 static inline void hisfc350_get_best_clock(unsigned int *clock) in hisfc350_get_best_clock() argument
88 if (*clock < sysclk[ix]) in hisfc350_get_best_clock()
93 *clock = clk_reg; in hisfc350_get_best_clock()
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| D | flash.h | 158 static inline void hifmc100_set_system_clock(unsigned clock, int clk_en) in hifmc100_set_system_clock() argument
166 if (clock) in hifmc100_set_system_clock()
167 regval |= clock & FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
185 static inline void hifmc100_get_best_clock(unsigned int *clock) in hifmc100_get_best_clock() argument
205 if (*clock < sys_2X_clk[ix]) in hifmc100_get_best_clock()
211 *clock = clk_reg; in hifmc100_get_best_clock()
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| /device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/ |
| D | spinand.h | 47 static void hisnfc100_set_system_clock(int clock, int clk_en) in hisnfc100_set_system_clock() argument
52 if (!clock) in hisnfc100_set_system_clock()
53 clock = SPI_NAND_CLK_SEL_75M; in hisnfc100_set_system_clock()
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
66 static void hisnfc100_get_best_clock(unsigned int *clock) in hisnfc100_get_best_clock() argument
81 if (*clock < sysclk[ix]) in hisnfc100_get_best_clock()
85 *clock = clk_reg; in hisnfc100_get_best_clock()
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| D | spinor.h | 50 static inline void hisfc350_set_system_clock(unsigned clock, int clk_en) in hisfc350_set_system_clock() argument
56 if (clock) { in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
72 static inline void hisfc350_get_best_clock(unsigned int *clock) in hisfc350_get_best_clock() argument
88 if (*clock < sysclk[ix]) in hisfc350_get_best_clock()
93 *clock = clk_reg; in hisfc350_get_best_clock()
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| /device/soc/rockchip/common/hardware/mpp/include/ |
| D | mpp_time.h | 42 void mpp_clock_put(MppClock clock);
43 void mpp_clock_enable(MppClock clock, unsigned int enable);
44 RK_S64 mpp_clock_start(MppClock clock);
45 RK_S64 mpp_clock_pause(MppClock clock);
46 RK_S64 mpp_clock_reset(MppClock clock);
47 RK_S64 mpp_clock_get_sum(MppClock clock);
48 RK_S64 mpp_clock_get_count(MppClock clock);
49 const char *mpp_clock_get_name(MppClock clock);
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| /device/soc/telink/b91/b91_ble_sdk/drivers/B91/ |
| D | s7816.c | 90 void s7816_init(uart_num_e uart_num, s7816_clock_e clock, int f, int d) in s7816_init() argument
94 s7816_clock = clock; in s7816_init()
95 s7816_rst_time = 40000 / clock; // us in s7816_init()
96 s7816_atr_time = 40000 / clock; // us in s7816_init()
98 int baud = clock * 1000000 * d / f; in s7816_init()
99 if (clock == S7816_4MHZ) { in s7816_init()
101 } else if (clock == S7816_6MHZ) { in s7816_init()
103 } else if (clock == S7816_12MHZ) { in s7816_init()
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| /device/soc/rockchip/rk3568/hardware/mpp/include/ |
| D | mpp_time.h | 42 void mpp_clock_put(MppClock clock);
43 void mpp_clock_enable(MppClock clock, RK_U32 enable);
44 RK_S64 mpp_clock_start(MppClock clock);
45 RK_S64 mpp_clock_pause(MppClock clock);
46 RK_S64 mpp_clock_reset(MppClock clock);
47 RK_S64 mpp_clock_get_sum(MppClock clock);
48 RK_S64 mpp_clock_get_count(MppClock clock);
49 const char *mpp_clock_get_name(MppClock clock);
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| /device/soc/rockchip/rk3588/hardware/mpp/include/ |
| D | mpp_time.h | 50 void mpp_clock_put(MppClock clock);
51 void mpp_clock_enable(MppClock clock, RK_U32 enable);
59 RK_S64 mpp_clock_start(MppClock clock);
60 RK_S64 mpp_clock_pause(MppClock clock);
61 RK_S64 mpp_clock_reset(MppClock clock);
69 RK_S64 mpp_clock_get_sum(MppClock clock);
70 RK_S64 mpp_clock_get_count(MppClock clock);
71 const char *mpp_clock_get_name(MppClock clock);
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| /device/soc/rockchip/rk3399/hardware/mpp/include/ |
| D | mpp_time.h | 49 void mpp_clock_put(MppClock clock);
50 void mpp_clock_enable(MppClock clock, RK_U32 enable);
58 RK_S64 mpp_clock_start(MppClock clock);
59 RK_S64 mpp_clock_pause(MppClock clock);
60 RK_S64 mpp_clock_reset(MppClock clock);
68 RK_S64 mpp_clock_get_sum(MppClock clock);
69 RK_S64 mpp_clock_get_count(MppClock clock);
70 const char *mpp_clock_get_name(MppClock clock);
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| D | Kconfig | 2 # common clock support for ROCKCHIP SoC family.
5 tristate "Rockchip RK3568 clock controller support"
12 tristate "Rockchip RK3588 clock controller support"
19 tristate "Rockchip RV1126 clock controller support"
26 tristate "Rockchip RK1808 clock controller support"
33 tristate "Rockchip clock link support"
36 Say y here to enable clock link for Rockchip.
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| /device/soc/amlogic/a311d/soc/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12b-unionpi-tiger.dtsi | 49 clock-latency = <50000>;
56 clock-latency = <50000>;
63 clock-latency = <50000>;
70 clock-latency = <50000>;
77 clock-latency = <50000>;
84 clock-latency = <50000>;
91 clock-names = "clkin0";
99 clock-names = "clkin1";
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| D | meson-g12.dtsi | 8 #include <dt-bindings/clock/axg-audio-clkc.h>
21 clock-names = "mclk", "sclk", "lrclk";
32 clock-names = "mclk", "sclk", "lrclk";
43 clock-names = "mclk", "sclk", "lrclk";
58 clock-names = "pclk", "dclk", "sysclk";
70 clkc_audio: clock-controller@0 {
74 #clock-cells = <1>;
86 clock-names = "pclk",
208 clock-names = "pclk", "sclk", "sclk_sel",
224 clock-names = "pclk", "sclk", "sclk_sel",
[all …]
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| /device/board/isoftstone/zhiyuan/bootloader/configs/zhiyuan/linux-5.10/ |
| D | board.dts | 472 #clock-cells = <0>;
473 compatible = "allwinner,pll-clock";
476 /*assigned-clock-rates = <432000000>;*/
477 clock-output-names = "pll_video2";
481 #clock-cells = <0>;
482 compatible = "allwinner,pll-clock";
484 assigned-clock-rates = <696000000>;
486 clock-output-names = "pll_de";
490 #clock-cells = <0>;
491 compatible = "allwinner,periph-clock";
[all …]
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| /device/soc/hisilicon/hi3518ev300/hdf_config/mtd/ |
| D | mtd_config.hcs | 24 clock = 0x0;
53 clock = 104;
60 clock = 104;
67 clock = 104;
78 clock = 0x0;
105 clock = 104;
112 clock = 104;
119 clock = 104;
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| /device/board/isoftstone/zhiyuan/bootloader/configs/default/linux-5.10/ |
| D | sun50iw9.dtsi | 6 #include <dt-bindings/clock/sun50iw9-ccu.h>
7 #include <dt-bindings/clock/sun50iw9-ccu-rtc.h>
8 #include <dt-bindings/clock/sun50iw9-r-ccu.h>
151 clock-latency-ns = <244144>; /* 8 32k periods */
158 clock-latency-ns = <244144>; /* 8 32k periods */
165 clock-latency-ns = <244144>; /* 8 32k periods */
172 clock-latency-ns = <244144>; /* 8 32k periods */
179 clock-latency-ns = <244144>; /* 8 32k periods */
187 clock-latency-ns = <244144>; /* 8 32k periods */
194 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/panel/ |
| D | panel-simple.c | 978 .clock = 71100,
1005 .clock = 9000,
1030 .clock = 33333,
1080 .clock = 51450,
1129 .clock = 72000,
1153 .clock = 69300,
1183 .clock = 70589,
1214 .clock = 69500,
1237 .clock = 150660,
1296 .clock = 68930,
[all …]
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| /device/board/kaihong/khdvk_3566b/kernel/ |
| D | rk3566-rp-kh.dts | 205 clock-latency-ns = <0x9c40>;
211 clock-latency-ns = <0x9c40>;
217 clock-latency-ns = <0x9c40>;
224 clock-latency-ns = <0x9c40>;
230 clock-latency-ns = <0x9c40>;
236 clock-latency-ns = <0x9c40>;
242 clock-latency-ns = <0x9c40>;
248 clock-latency-ns = <0x9c40>;
345 #clock-cells = <0x01>;
469 external-gmac0-clock {
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/gpu/panfrost/ |
| D | panfrost_device.c | 86 pfdev->clock = of_clk_get_by_name(pfdev->dev->of_node, "clk_mali"); in panfrost_clk_init()
87 if (!IS_ERR_OR_NULL(pfdev->clock)) { in panfrost_clk_init()
88 clk_set_rate(pfdev->clock, rate); in panfrost_clk_init()
89 err = clk_prepare_enable(pfdev->clock); in panfrost_clk_init()
95 return PTR_ERR(pfdev->clock); in panfrost_clk_init()
118 pfdev->clock = devm_clk_get(pfdev->dev, NULL); in panfrost_clk_init()
119 if (IS_ERR(pfdev->clock)) { in panfrost_clk_init()
120 dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock)); in panfrost_clk_init()
121 return PTR_ERR(pfdev->clock); in panfrost_clk_init()
124 rate = clk_get_rate(pfdev->clock); in panfrost_clk_init()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/ |
| D | vin.c | 162 vind->clk[VIN_TOP_CLK].clock = devm_clk_get(dev, "csi_top"); in vin_md_get_clocks()
163 if (IS_ERR(vind->clk[VIN_TOP_CLK].clock)) { in vin_md_get_clocks()
165 return PTR_ERR(vind->clk[VIN_TOP_CLK].clock); in vin_md_get_clocks()
167 vind->clk[VIN_TOP_CLK_SRC].clock = devm_clk_get(dev, "csi_top_src"); in vin_md_get_clocks()
168 if (IS_ERR(vind->clk[VIN_TOP_CLK_SRC].clock)) { in vin_md_get_clocks()
170 return PTR_ERR(vind->clk[VIN_TOP_CLK_SRC].clock); in vin_md_get_clocks()
194 vind->isp_clk[VIN_ISP_CLK].clock = devm_clk_get(dev, "csi_isp"); in vin_md_get_clocks()
195 if (IS_ERR(vind->isp_clk[VIN_ISP_CLK].clock)) { in vin_md_get_clocks()
196 vind->isp_clk[VIN_ISP_CLK].clock = NULL; in vin_md_get_clocks()
199 vind->isp_clk[VIN_ISP_CLK_SRC].clock = devm_clk_get(dev, "csi_isp_src"); in vin_md_get_clocks()
[all …]
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/ |
| D | mali_dvfs_policy.c | 85 if (((int)(gpu_clk->item[i].clock) - target_clock_mhz) > 0) { in mali_pickup_closest_avail_clock()
182 …target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util * mali_desired_fps / under_p… in mali_dvfs_policy_realize()
186 …target_clk_mhz = gpu_clk->item[cur_clk_step].clock * current_gpu_util / under_perform_boundary_val… in mali_dvfs_policy_realize()
202 gpu_clk->item[clock_step].clock, in mali_dvfs_policy_realize()
235 i, gpu_clk->item[i].clock, gpu_clk->item[i].vol)); in mali_dvfs_policy_init()
276 …PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, gpu_clk->item[gpu_clk->num_of_steps - 1].clock, in mali_dvfs_policy_new_period()
300 clk_item->clock = mali_gpu_clk->item[cur_clk_step].clock; in mali_get_current_gpu_clk_item()
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| D | Kconfig | 2 # common clock support for ROCKCHIP SoC family.
6 tristate "Rockchip RV1126 clock controller support"
13 tristate "Rockchip RK1808 clock controller support"
20 tristate "Rockchip RK3568 clock controller support"
|