Searched refs:src1_mmu_flag (Results 1 – 12 of 12) sorted by relevance
593 if (req->mmu_info.src1_mmu_flag & 1) { in rga2_mmu_info_BitBlt_mode()802 req->mmu_info.src1_mmu_flag = in rga2_mmu_info_BitBlt_mode()861 req->mmu_info.src1_mmu_flag = 0; in rga2_mmu_info_color_palette_mode()1157 req->mmu_info.src1_mmu_flag = in rga2_mmu_info_update_palette_table_mode()1158 req->mmu_info.src1_mmu_flag == in rga2_mmu_info_update_palette_table_mode()1159 1 ? 0 : req->mmu_info.src1_mmu_flag; in rga2_mmu_info_update_palette_table_mode()
1623 ((msg->mmu_info.src1_mmu_flag & 0xf) << 4) | in RGA2_set_mmu_reg_info()1925 req->mmu_info.src1_mmu_flag = in rga_cmd_to_rga2_cmd()1949 req->mmu_info.src1_mmu_flag = 0; in rga_cmd_to_rga2_cmd()2294 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, in print_debug_info()2337 if ((req.mmu_info.src0_mmu_flag & 1) || (req.mmu_info.src1_mmu_flag & 1) in rga2_init_reg()
1573 req->mmu_info.src1_mmu_flag = 1; in rga_cmd_to_rga3_cmd()1948 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, in print_debug_info()
385 mmu_flag = req->mmu_info.src1_mmu_flag; in rga2_get_dma_info()1083 if (req->mmu_info.src1_mmu_flag & 1) { in rga2_mmu_info_BitBlt_mode()1222 req->mmu_info.src1_mmu_flag = req->mmu_info.dst_mmu_flag; in rga2_mmu_info_BitBlt_mode()1267 req->mmu_info.src1_mmu_flag = 0; in rga2_mmu_info_color_palette_mode()1479 … req->mmu_info.src1_mmu_flag = req->mmu_info.src1_mmu_flag == 1 ? 0 : req->mmu_info.src1_mmu_flag; in rga2_mmu_info_update_palette_table_mode()
1421 …reg = (msg->mmu_info.src0_mmu_flag & 0xf) | ((msg->mmu_info.src1_mmu_flag & 0xf) << RGA2_INDEX_FO)… in RGA2_set_mmu_info()1861 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> RGA2_INDEX_NI) & 1); in RGA_MSG_2_RGA2_MSG()1878 req->mmu_info.src1_mmu_flag = 0; in RGA_MSG_2_RGA2_MSG()2123 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> RGA2_INDEX_NI) & 1); in RGA_MSG_2_RGA2_MSG_32()2140 req->mmu_info.src1_mmu_flag = 0; in RGA_MSG_2_RGA2_MSG_32()
182 …u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir… member
345 … src=%.2x src1=%.2x dst=%.2x els=%.2x\n", req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, in print_debug_info()772 …if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) || (req->mmu_info.dst_m… in rga2_reg_init()995 …if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) || (req->mmu_info.dst_m… in rga2_blit_flush_cache()
414 mmu_flag = req->mmu_info.src1_mmu_flag; in rga2_get_dma_info()1177 if (req->mmu_info.src1_mmu_flag & 1) { in rga2_mmu_info_BitBlt_mode()1355 req->mmu_info.src1_mmu_flag = req->mmu_info.dst_mmu_flag; in rga2_mmu_info_BitBlt_mode()1400 req->mmu_info.src1_mmu_flag = 0; in rga2_mmu_info_color_palette_mode()1634 … req->mmu_info.src1_mmu_flag = req->mmu_info.src1_mmu_flag == 1 ? 0 : req->mmu_info.src1_mmu_flag; in rga2_mmu_info_update_palette_table_mode()
1048 reg = (msg->mmu_info.src0_mmu_flag & 0xf) | ((msg->mmu_info.src1_mmu_flag & 0xf) << 4) in RGA2_set_mmu_info()1402 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1); in RGA_MSG_2_RGA2_MSG()1420 req->mmu_info.src1_mmu_flag = 0; in RGA_MSG_2_RGA2_MSG()1666 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1); in RGA_MSG_2_RGA2_MSG_32()1684 req->mmu_info.src1_mmu_flag = 0; in RGA_MSG_2_RGA2_MSG_32()
179 …u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch… member
351 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, in print_debug_info()793 if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) in rga2_reg_init()1027 if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) || in rga2_blit_flush_cache()
212 u8 src1_mmu_flag; member