| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 8 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
16 if (unlikely(pll->pll_on)) in dsi_pll_enable()
20 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
21 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
33 pll->pll_on = true; in dsi_pll_enable()
38 static void dsi_pll_disable(struct msm_dsi_pll *pll) in dsi_pll_disable() argument
40 if (unlikely(!pll->pll_on)) in dsi_pll_disable()
43 pll->disable_seq(pll); in dsi_pll_disable()
45 pll->pll_on = false; in dsi_pll_disable()
54 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in msm_dsi_pll_helper_clk_round_rate() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
65 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
72 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
89 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) in __mtk_pll_tuner_enable() argument
93 if (pll->tuner_en_addr) { in __mtk_pll_tuner_enable()
94 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); in __mtk_pll_tuner_enable()
95 writel(r, pll->tuner_en_addr); in __mtk_pll_tuner_enable()
96 } else if (pll->tuner_addr) { in __mtk_pll_tuner_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-pll.c | 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
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| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | pll.c | 18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
29 GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
30 pshift(pll, member)) : 0)
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
127 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
130 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
136 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
142 if (pll->xres != 0) { in aty_dsp_gt()
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
167 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
189 #define wait_for_pll_enable_active(pll) \ argument
190 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
192 #define wait_for_pll_enable_lock(pll) \ argument
193 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
195 #define wait_for_pll_disable(pll) \ argument
196 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
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| D | clk-pll.c | 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
87 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pllv3.c | 60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
62 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
65 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
68 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, in clk_pllv3_wait_lock()
74 struct clk_pllv3 *pll = to_clk_pllv3(hw); in clk_pllv3_prepare() local
77 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
78 if (pll->powerup_set) in clk_pllv3_prepare()
79 val |= pll->power_bit; in clk_pllv3_prepare()
81 val &= ~pll->power_bit; in clk_pllv3_prepare()
82 writel_relaxed(val, pll->base); in clk_pllv3_prepare()
[all …]
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| D | clk-pll14xx.c | 90 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
92 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
95 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
105 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll14xx_round_rate() local
106 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in clk_pll14xx_round_rate()
110 for (i = 0; i < pll->rate_count; i++) in clk_pll14xx_round_rate()
121 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll1416x_recalc_rate() local
125 pll_div = readl_relaxed(pll->base + 4); in clk_pll1416x_recalc_rate()
139 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll1443x_recalc_rate() local
144 pll_div_ctl0 = readl_relaxed(pll->base + 4); in clk_pll1443x_recalc_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 85 struct iproc_pll *pll; member
128 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
132 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
133 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
136 if (i >= pll->num_vco_entries) in pll_get_rate_index()
157 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
160 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
163 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
173 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, in iproc_pll_write() argument
176 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write()
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| D | clk-iproc-armpll.c | 76 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
81 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
90 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
94 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
116 static int __get_mdiv(struct iproc_arm_pll *pll) in __get_mdiv() argument
122 fid = __get_fid(pll); in __get_mdiv()
131 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
138 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
151 static unsigned int __get_ndiv(struct iproc_arm_pll *pll) in __get_ndiv() argument
156 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); in __get_ndiv()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | smiapp-pll.c | 53 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
55 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
56 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
57 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
58 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
59 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
61 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
62 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
64 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); in print_pll()
65 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); in print_pll()
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| D | aptina-pll.c | 18 struct aptina_pll *pll) in aptina_pll_calculate() argument
28 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
30 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
31 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
36 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
42 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
43 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
44 div = pll->ext_clock / div; in aptina_pll_calculate()
56 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); in aptina_pll_calculate()
58 (pll->ext_clock / limits->n_min * pll->m)); in aptina_pll_calculate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-pll.c | 46 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) in __pll_round_closest_mult() argument
48 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && in __pll_round_closest_mult()
49 !MESON_PARM_APPLICABLE(&pll->frac)) in __pll_round_closest_mult()
58 struct meson_clk_pll_data *pll) in __pll_params_to_rate() argument
62 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
66 (1 << pll->frac.width)); in __pll_params_to_rate()
76 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); in meson_clk_pll_recalc_rate() local
79 n = meson_parm_read(clk->map, &pll->n); in meson_clk_pll_recalc_rate()
89 m = meson_parm_read(clk->map, &pll->m); in meson_clk_pll_recalc_rate()
91 frac = MESON_PARM_APPLICABLE(&pll->frac) ? in meson_clk_pll_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/x86/ |
| D | clk-cgu-pll.c | 41 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_recalc_rate()
46 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
47 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
48 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 spin_unlock_irqrestore(&pll->lock, flags); in lgm_pll_recalc_rate()
51 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
59 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_is_enabled() local
63 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_is_enabled()
64 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); in lgm_pll_is_enabled()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-pll.c | 51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
88 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
93 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/pistachio/ |
| D | clk-pll.c | 78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
80 return readl(pll->base + reg); in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
85 writel(val, pll->base + reg); in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
110 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; in pll_frac_get_mode()
116 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_set_mode() local
119 val = pll_readl(pll, PLL_CTRL3); in pll_frac_set_mode()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
121 spin_lock_irqsave(&pll->lock, flags); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
123 ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw), in ccu_pll_enable()
125 spin_unlock_irqrestore(&pll->lock, flags); in ccu_pll_enable()
134 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_disable() local
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-pll.c | 36 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
53 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
57 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
68 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
71 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
72 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
73 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_pll.c | 23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
41 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
45 r = pm_runtime_get_sync(&pll->pdev->dev); in hdmi_pll_enable()
59 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
67 r = pm_runtime_put_sync(&pll->pdev->dev); in hdmi_pll_disable()
132 struct dss_pll *pll = &hpll->pll; in hdmi_init_pll_data() local
142 pll->name = "hdmi"; in hdmi_init_pll_data()
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| /kernel/linux/linux-5.10/drivers/clk/st/ |
| D | clkgen-pll.c | 168 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
169 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
176 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
177 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
183 struct clkgen_pll *pll = to_clkgen_pll(hw); in __clkgen_pll_enable() local
184 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
185 struct clkgen_field *field = &pll->data->locked_status; in __clkgen_pll_enable()
192 CLKGEN_WRITE(pll, pdn_ctrl, 0); in __clkgen_pll_enable()
198 if (pll->data->switch2pll_en) in __clkgen_pll_enable()
199 CLKGEN_WRITE(pll, switch2pll, 0); in __clkgen_pll_enable()
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-pll.c | 31 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_is_enabled() local
34 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_is_enabled()
35 if ((val & pll->enable) == pll->enable) in mmp_clk_pll_is_enabled()
39 if (pll->default_rate > 0) in mmp_clk_pll_is_enabled()
48 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_recalc_rate() local
53 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_recalc_rate()
54 if ((val & pll->enable) != pll->enable) in mmp_clk_pll_recalc_rate()
55 return pll->default_rate; in mmp_clk_pll_recalc_rate()
57 if (pll->reg) { in mmp_clk_pll_recalc_rate()
58 val = readl_relaxed(pll->reg); in mmp_clk_pll_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/at91/ |
| D | clk-pll.c | 56 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
57 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
58 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
60 pll->characteristics; in clk_pll_prepare()
61 u8 id = pll->id; in clk_pll_prepare()
76 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
80 out = characteristics->out[pll->range]; in clk_pll_prepare()
84 characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); in clk_pll_prepare()
87 pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | in clk_pll_prepare()
89 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
398 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_set_clk_rate() local
399 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8996_pll_set_clk_rate()
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| /kernel/linux/linux-5.10/drivers/clk/mxs/ |
| D | clk-pll.c | 34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
61 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
63 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
69 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
71 return pll->rate; in clk_pll_recalc_rate()
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