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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc-qcs404.yaml49 reg = <0x01800000 0x80000>;
Dqcom,gcc-ipq8074.yaml49 reg = <0x01800000 0x80000>;
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Danubis.h17 #define ANUBIS_CTRL1_NANDSEL (0x3)
21 #define ANUBIS_IDREG_REVMASK (0x7)
33 #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
39 #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
42 #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
45 #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
46 #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
47 #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
48 #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
Dbast.h16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)
17 #define BAST_CPLD_CTRL1_LRCADC (0x01)
18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)
19 #define BAST_CPLD_CTRL1_LRCARM (0x03)
20 #define BAST_CPLD_CTRL1_LRMASK (0x03)
24 #define BAST_CPLD_CTRL2_WNAND (0x04)
25 #define BAST_CPLD_CTLR2_IDERST (0x08)
29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)
30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)
34 #define BAST_CPLD_CTRL4_LLAT (0x01)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8822bwifionly.c9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dzeus.h21 #define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000)
23 #define ZEUS_PC104IO_PHYS (0x30000000)
25 #define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000)
26 #define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000)
27 #define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000)
28 #define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000)
31 #define ZEUS_AC97_GPIO 0
68 #define ZEUS_CPLD IOMEM(0xf0000000)
69 #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000)
70 #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000)
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
34 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
38 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
39 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
[all …]
Dk3-j721e-som-p0.dtsi14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa6000000 0x00 0x100000>;
37 reg = <0x00 0xa6100000 0x00 0xf00000>;
43 reg = <0x00 0xa7000000 0x00 0x100000>;
49 reg = <0x00 0xa7100000 0x00 0xf00000>;
55 reg = <0x00 0xa8000000 0x00 0x100000>;
61 reg = <0x00 0xa8100000 0x00 0xf00000>;
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/sn/sn0/
Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dtraps.h29 #define VEC_RESETSP (0)
100 #define PS_T (0x8000)
101 #define PS_S (0x2000)
102 #define PS_M (0x1000)
103 #define PS_C (0x0001)
107 #define FC (0x8000)
108 #define FB (0x4000)
109 #define RC (0x2000)
110 #define RB (0x1000)
111 #define DF (0x0100)
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/
Dsdk7780.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0xa0800000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
23 #define PA_SDRAM_SIZE 0x08000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-se/mach/
Dse7722.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
23 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE 0x04000000
26 #define PA_EXT4 0xb0000000
27 #define PA_EXT4_SIZE 0x04000000
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-rc32434/
Dddr.h49 #define DDR0_PHYS_ADDR 0x18018000
52 #define DDR_MASK 0xffff0000
58 #define RC32434_DDR0_ATA_MSK 0x000000E0
60 #define RC32434_DDR0_DBW_MSK 0x00000100
62 #define RC32434_DDR0_WR_MSK 0x00000600
64 #define RC32434_DDR0_PS_MSK 0x00001800
66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000
68 #define RC32434_DDR0_RFC_MSK 0x000f0000
70 #define RC32434_DDR0_RP_MSK 0x00300000
72 #define RC32434_DDR0_AP_MSK 0x00400000
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/ip32/
Dcrime.h18 #define CRIME_BASE 0x14000000 /* physical */
22 #define CRIME_ID_MASK 0xff
23 #define CRIME_ID_IDBITS 0xf0
24 #define CRIME_ID_IDVALUE 0xa0
25 #define CRIME_ID_REV 0x0f
26 #define CRIME_REV_PETTY 0x00
27 #define CRIME_REV_11 0x11
28 #define CRIME_REV_13 0x13
29 #define CRIME_REV_14 0x14
32 #define CRIME_CONTROL_MASK 0x3fff
[all …]
/kernel/linux/linux-5.10/sound/soc/amd/
Dacp.h8 #define ACP_PAGE_SIZE_4K_ENABLE 0x02
11 #define ACP_CAPTURE_PTE_OFFSET 0
14 #define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
15 #define ACP_ST_CAPTURE_PTE_OFFSET 0x00
16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08
17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c
19 #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
20 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
22 #define ACP_PHYSICAL_BASE 0x14000
32 #define ACP_SRAM_BANK_1_ADDRESS 0x4002000
[all …]
/kernel/linux/linux-5.10/sound/soc/sh/rcar/
Dsrc.c41 for ((i) = 0; \
59 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
66 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
88 return 0; in rsnd_src_convert_rate()
110 unsigned int rate = 0; in rsnd_src_get_rate()
138 0x01800000, /* 6 - 1/6 */
139 0x01000000, /* 6 - 1/4 */
140 0x00c00000, /* 6 - 1/3 */
141 0x00800000, /* 6 - 1/2 */
142 0x00600000, /* 6 - 2/3 */
[all …]
/kernel/linux/linux-5.10/arch/mips/sgi-ip27/
Dip27-xtalk.c22 #define XBOW_WIDGET_PART_NUM 0x0
23 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */
46 memset(&w1_res, 0, sizeof(w1_res)); in bridge_platform_create()
85 bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD; in bridge_platform_create()
143 pr_info("xtalk:n%d/%d unknown widget (0x%x)\n", in probe_one_port()
148 return 0; in probe_one_port()
199 return 0; in xbow_probe()
215 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); in xtalk_probe_node()
220 bridge_platform_create(nasid, 0x8, 0xa); in xtalk_probe_node()
224 pr_info("xtalk:n%d/0 xbow widget\n", nasid); in xtalk_probe_node()
[all …]
/kernel/linux/linux-5.10/include/linux/
Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/kernel/linux/linux-5.10/drivers/mtd/devices/
Dms02-nv.c26 "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n";
35 * at any 8MiB boundary within a 0MiB up to 112MiB range or at any 32MiB
36 * boundary within a 0MiB up to 448MiB range. We don't support a module
37 * at 0MiB, though.
40 0x07000000, 0x06800000, 0x06000000, 0x05800000, 0x05000000,
41 0x04800000, 0x04000000, 0x03800000, 0x03000000, 0x02800000,
42 0x02000000, 0x01800000, 0x01000000, 0x00800000
60 return 0; in ms02nv_read()
70 return 0; in ms02nv_write()
92 return 0; in ms02nv_probe_one()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkirkwood-l-50.dts18 reg = <0x00000000 0x20000000>;
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
69 reg = <0x20>;
74 /* Three GPIOs from 0x21 exp. are undescribed in dts:
83 reg = <0x21>;
90 reg = <0x30>;
126 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
206 reg = <0x08>;
212 #size-cells = <0>;
213 reg = <0x10>;
[all …]
/kernel/linux/linux-5.10/sound/pci/asihpi/
Dhpi6205.c56 #define C6205_HSR_INTSRC 0x01
57 #define C6205_HSR_INTAVAL 0x02
58 #define C6205_HSR_INTAM 0x04
59 #define C6205_HSR_CFGERR 0x08
60 #define C6205_HSR_EEREAD 0x10
62 #define C6205_HDCR_WARMRESET 0x01
63 #define C6205_HDCR_DSPINT 0x02
64 #define C6205_HDCR_PCIBOOT 0x04
67 #define C6205_DSPP_MAP1 0x400
71 * of DSP memory mapped registers (starting at 0x01800000).
[all …]

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