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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
22 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
25 partition@0 {
27 reg = <0x0 0x300000>;
32 reg = <0x300000 0x80000>;
37 reg = <0x380000 0x80000>;
42 reg = <0x400000 0x80000>;
47 reg = <0x480000 0x80000>;
52 reg = <0x500000 0x800000>;
57 reg = <0xd00000 0xf300000>;
[all …]
Dimx27-apf27.dts18 reg = <0xa0000000 0x04000000>;
23 clock-frequency = <0>;
30 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
31 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
32 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
33 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
34 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
35 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
36 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
37 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
[all …]
Domap3430-sdp.dts15 reg = <0x80000000 0x10000000>; /* 256 MB */
23 reg = <0x48>;
50 ranges = <0 0 0x10000000 0x08000000>,
51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
52 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
54 nor@0,0 {
59 reg = <0 0 0x08000000>;
63 gpmc,cs-on-ns = <0>;
84 partition@0 {
86 reg = <0 0x40000>;
[all …]
Daspeed-bmc-ibm-rainier.dts42 reg = <0x80000000 0x40000000>;
52 reg = <0xB8000000 0x04000000>; /* 64M */
58 reg = <0xbf000000 0x01000000>; /* 16M */
67 gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
68 linux,code = <ASPEED_GPIO(S, 0)>;
93 #size-cells = <0>;
99 idle-state = <0>;
101 i2c2mux0: i2c@0 {
103 #size-cells = <0>;
104 reg = <0>;
[all …]
Dkeystone-k2e-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #clock-cells = <0>;
83 reg = <0x50>;
94 ti,cs-chipselect = <0>;
104 nand@0,0 {
108 reg = <0 0 0x4000000
109 1 0 0x0000100>;
111 ti,davinci-chipselect = <0>;
[all …]
Dkeystone-k2l-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
33 #clock-cells = <0>;
56 reg = <0x50>;
67 ti,cs-chipselect = <0>;
77 nand@0,0 {
81 reg = <0 0 0x4000000
82 1 0 0x0000100>;
84 ti,davinci-chipselect = <0>;
85 ti,davinci-mask-ale = <0x2000>;
86 ti,davinci-mask-cle = <0x4000>;
[all …]
Darmada-380.dtsi20 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
46 bus-range = <0x00 0xff>;
49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
Dorion5x-lacie-ethernet-disk-mini-v2.dts29 reg = <0x00000000 0x4000000>; /* 64 MB */
38 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
39 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
40 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
45 pinctrl-0 = <&pmx_power_button>;
48 #size-cells = <0>;
58 pinctrl-0 = <&pmx_power_led>;
74 devbus,badr-skew-ps = <0>;
93 flash@0 {
95 reg = <0 0x80000>;
[all …]
Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
32 reg = <0x4b2a6000 0x4>,
33 <0x4b2a6004 0x4>;
44 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
48 ranges = <0x00000000 0x4b280000 0x80000>;
Dkirkwood-6282.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
23 pcie0: pcie@1,0 {
25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
[all …]
Ddm8148-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
Dpicoxcell-pc7302-pc3x2.dts14 reg = <0x0 0x08000000>;
31 nand: gpio-nand@2,0 {
35 reg = <2 0x0000 0x1000>;
38 <0x00000000 0x80220000>;
40 gpios = <&banka 1 0 /* rdy */
41 &banka 2 0 /* nce */
42 &banka 3 0 /* ale */
43 &banka 4 0 /* cle */
44 0 /* nwp */>;
48 reg = <0x100000 0x80000>;
[all …]
Dpicoxcell-pc7302-pc3x3.dts14 reg = <0x0 0x08000000>;
37 nand: gpio-nand@2,0 {
41 reg = <2 0x0000 0x1000>;
44 <0x00000000 0x80220000>;
46 gpios = <&banka 1 0 /* rdy */
47 &banka 2 0 /* nce */
48 &banka 3 0 /* ale */
49 &banka 4 0 /* cle */
50 0 /* nwp */>;
54 reg = <0x100000 0x80000>;
[all …]
Darmada-385.dtsi20 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
45 bus-range = <0x00 0xff>;
48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
Dspear320-hmi.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
102 partition@0 {
104 reg = <0x0 0x80000>;
108 reg = <0x80000 0x140000>;
112 reg = <0x1C0000 0x40000>;
116 reg = <0x200000 0x40000>;
120 reg = <0x240000 0xC00000>;
124 reg = <0xE40000 0x0>;
131 #size-cells = <0>;
[all …]
Dkeystone-k2hk-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
111 ti,cs-chipselect = <0>;
121 nand@0,0 {
125 reg = <0 0 0x4000000
126 1 0 0x0000100>;
[all …]
Dorion5x-lacie-d2-network.dts23 reg = <0x00000000 0x4000000>; /* 64 MB */
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
33 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
34 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
39 pinctrl-0 = <&pmx_buttons>;
42 #size-cells = <0>;
67 #size-cells = <0>;
68 pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>;
71 sata0_power: regulator@0 {
73 reg = <0>;
[all …]
Dbcm7445.dtsi17 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
50 reg = <0x00 0xffd01000 0x00 0x1000>,
51 <0x00 0xffd02000 0x00 0x2000>,
52 <0x00 0xffd04000 0x00 0x2000>,
53 <0x00 0xffd06000 0x00 0x2000>;
70 ranges = <0 0x00 0xf0000000 0x1000000>;
74 reg = <0x40ab00 0x20>;
84 reg = <0x404000 0x51c>;
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dtpc0_cfg_masks.h23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/ip32/
Dmace.h18 #define MACE_BASE 0x1f000000 /* physical */
43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST 0
45 #define MACEPCI_ERROR_DEVSEL_MED 0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
48 #define MACEPCI_ERROR_66MHZ BIT(0)
51 #define MACEPCI_CONTROL_INT_MASK 0xff
61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
71 unsigned int _pad[0xcf8/4 - 4];
79 #define MACEPCI_LOW_MEMORY 0x1a000000
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi10 #clock-cells = <0>;
17 #clock-cells = <0>;
24 #clock-cells = <0>;
31 #clock-cells = <0>;
38 reg = <0 0xe0700000 0 0x80000>,
39 <0 0xe0780000 0 0x80000>,
40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
43 interrupts = <0 325 4>,
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/
Dmcu.h12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dimx-rproc.txt21 reg = <0x80000000 0x80000>;
25 reg = <0x81000000 0x80000>;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]

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